fix(PTW): should not do pmp check before G-stage finish (#4524)

In https://github.com/OpenXiangShan/XiangShan/pull/4422, For the
virtualized allStage scenario, we attempt to suppress PMP checks unti

fix(PTW): should not do pmp check before G-stage finish (#4524)

In https://github.com/OpenXiangShan/XiangShan/pull/4422, For the
virtualized allStage scenario, we attempt to suppress PMP checks until
the G-stage translation result is returned. However, the approach used
in https://github.com/OpenXiangShan/XiangShan/pull/4422 is to try
ignoring the `accessFault` result when `io.hptw.req.valid` is asserted.

In reality, the `accessFault` signal remains valid because it is
implemented as a `RegEnable`. Therefore, we need to prevent
`sent_to_pmp` from being asserted when sending the G-stage translation
request to HPTW. To address this, we introduce the `vs_finish` signal.
When `vs_finish` is `true.B`, `sent_to_pmp` will be false, thus avoiding
false `accessFault` reports.

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fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 T

fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 TLB. When
`req_need_gpa` is valid, it is sufficient to send an onlyStage1 request
to obtain the guest physical address.

In the original design, multiple cases in the `MuxCase` could be valid
at the same time. For example, when both `csr.vsatp.mode =/= 0.U` and
`csr.hgatp.mode =/= 0.U` are valid, an allStage request would be sent
directly, without considering the `req_need_gpa` condition. This commit
fixes that bug.

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fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstransla

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstranslation caches by executing an
> SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA,
> HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and
> optionally ASIDs or VMIDs) in question, and then executing an
> SFENCE.INVAL.IR instruction.

Some additional information was obtained through
https://github.com/riscv/riscv-isa-manual/issues/1936

However, other instructions may still appear between SFENCE.W.INVAL and
SFENCE.INVAL.IR.
> Translation of any memory accesses during that sequence are subject to
> the usual uncertainty as to which translation (among old and new ones)
> is used.

Moreover, these memory accesses are not entirely unpredictable either.
> Each subsequent memory access will unpredictably use either the old
> translation or the new translation. Other behaviors can't occur.

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fix(difftest): fix sync aia event valid (#4517)

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the c

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the clock

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fix(CSR): use GEILEN from IMSICParams (#4520)

fix(XSTileWrap): remove useless IMSICAsync (#4515)

Already included in CSR.

fix(Uncache): uncache mm store needs difftest to update goldenmem (#4470)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(AIA): integrate ChiselAIA again (#4509)

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secur

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secure), allowing XiangShan core to function as a secure boot processor
in NoC. For systems that already utilize an MCU for secure boot, access
of XiangShan core should theoretically be non-secure. In the latter
cases, `ENABLE_NS=1` option should be added to the `make` compilation
command.

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chore(XSNoCTop): minor connection changes (#4501)

chore(XSNoCTop): change to dft and dft_reset io (#4502)

feat(backend): make wfi timeout configurable (#4491)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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fix(Config): turn on mbist in Default, KunminghuV2 and XSNoCTop Config (#4497)

fix(FTB, FTQ): dont use CPL2 SplittedSRAM (#4485)

If the frontend directly uses the SplittedSRAM of coupledL2, the
frontend's SRAM will be marked as a multi-cycle path, the same as
coupledL2's SRAM.

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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fix(AXI4Memory): remove `AWLEN == 0` Check (#4383)

fix(MMU): unify vmid matching logic (#4484)

In scenarios where virtualisation is turned on, either onlyS1, onlyS2,
or allStage, vmid matching is required. Specifically:

onlyS2: s2.vmid
onlyS1 or al

fix(MMU): unify vmid matching logic (#4484)

In scenarios where virtualisation is turned on, either onlyS1, onlyS2,
or allStage, vmid matching is required. Specifically:

onlyS2: s2.vmid
onlyS1 or allStage: s1.vmid

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fix(PTW): fix gpf_level generate logic when Sv39 (#4482)

For historical reasons, `gpf_level` needs to be 1 greater than
`af_level`. In the original design, only the Sv48 case was considered,
and a s

fix(PTW): fix gpf_level generate logic when Sv39 (#4482)

For historical reasons, `gpf_level` needs to be 1 greater than
`af_level`. In the original design, only the Sv48 case was considered,
and a similar treatment is needed for the Sv39 case.

As an extra note here, `gpf_level` is a 2-bit register, so when
`gpf_level` = 0.U, `gpf_level` - 2.U = `00` - 2 = `10` = 2.U. The PTW
module's `gpf_level` computation uses this feature, which is extremely
unscalable, and, except for the original author, is completely
incomprehensible, and is in dire need of refactoring.

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fix(PTW): fix gvpn check when req first enter PTW (#4481)

In the previous design, we used `gvpn_gpf` to detect whether the G-Stage
meets the gvpn high level of 0 after the VS-Stage translation is
co

fix(PTW): fix gvpn check when req first enter PTW (#4481)

In the previous design, we used `gvpn_gpf` to detect whether the G-Stage
meets the gvpn high level of 0 after the VS-Stage translation is
completed in allStage case, or else a guest page fault is reported.

However, due to some historical reasons, `gvpn_gpf` can only be used to
detect guest faults during the translation process; for the first time
when entering the PTW after the request to query the Page Table Cache
has finished, similar error checking will be done in
`check_gpa_high_fail`, but when the PTW resp valid is 1, the error
checking will be done in `check_gpa_high_fail`, `full_gvpn` has been
cleared to 0 (line 374), so `gvpn_gpf` will not be 1 (should be 1),
resulting in an error in the returned message.

I do not know why it was designed this way at the time, so I had to add
another `first_gvpn_check_fail` signal to indicate that the first
request into the PTW didn't satisfy the gvpn's high level check, and
therefore needed to report a guest page fault.

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fix(MainPipe): fix error valid generate logic (#4480)

* Atomics and Sbuffer write request should not report error

fix(MainPipe): fix tag match logic when ecc inject occur (#4479)

* When ecc injection occurs, it is necessary to determine whether there
is a hit cacheline in the `TagArray`. For example, `prefetch.

fix(MainPipe): fix tag match logic when ecc inject occur (#4479)

* When ecc injection occurs, it is necessary to determine whether there
is a hit cacheline in the `TagArray`. For example, `prefetch.w` will be
refilled due to permission mismatch. At this time, there is a hit
cacheline in the `TagArray`. If there is a hit way, it is necessary to
select the way, otherwise select the way determined by replacement.

* It's necessary to determine whether there is a hit with a non-toggle
tag.

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fix(LoadUnit): not enter misalignbuffer on exception (#4477)