xref: /XiangShan/src/main/scala/xiangshan/L2Top.scala (revision 602aa9f1a8fb63310bea30e8b3e247e5aca5f123) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.devices.debug.DebugModuleKey
24import freechips.rocketchip.diplomacy._
25import freechips.rocketchip.interrupts._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
27import freechips.rocketchip.tilelink._
28import device.MsiInfoBundle
29import coupledL2.{EnableCHI, L2ParamKey, PrefetchCtrlFromCore}
30import coupledL2.tl2tl.TL2TLCoupledL2
31import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
32import huancun.BankBitsKey
33import system.HasSoCParameter
34import top.BusPerfMonitor
35import utility._
36import utility.sram.SramMbistBundle
37import xiangshan.cache.mmu.TlbRequestIO
38import xiangshan.backend.fu.PMPRespBundle
39import xiangshan.backend.trace.{Itype, TraceCoreInterface}
40
41class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
42  val ecc_error = Valid(UInt(soc.PAddrBits.W))
43}
44
45class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
46  val icache = new L1BusErrorUnitInfo
47  val dcache = new L1BusErrorUnitInfo
48  val l2 = new L1BusErrorUnitInfo
49
50  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
51    List(
52      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
53      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
54      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
55    )
56}
57
58/**
59  *   L2Top contains everything between Core and XSTile-IO
60  */
61class L2TopInlined()(implicit p: Parameters) extends LazyModule
62  with HasXSParameter
63  with HasSoCParameter
64{
65  override def shouldBeInlined: Boolean = true
66
67  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
68    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
69    buffers.zipWithIndex.foreach{ case (b, i) => {
70      b.suggestName(s"${n}_${i}")
71    }}
72    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
73    (buffers, node)
74  }
75  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
76  // =========== Components ============
77  val l1_xbar = TLXbar()
78  val mmio_xbar = TLXbar()
79  val mmio_port = TLIdentityNode() // to L3
80  val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode())
81  val beu = LazyModule(new BusErrorUnit(
82    new XSL1BusErrors(),
83    BusErrorUnitParams(soc.BEURange.base, soc.BEURange.mask.toInt + 1)
84  ))
85
86  val i_mmio_port = TLTempNode()
87  val d_mmio_port = TLTempNode()
88  val icachectrl_port_opt = Option.when(icacheParameters.cacheCtrlAddressOpt.nonEmpty)(TLTempNode())
89  val sep_dm_port_opt = Option.when(SeperateDMBus)(TLTempNode())
90
91  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW
92  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
93  val xbar_l2_buffer = TLBuffer()
94
95  val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB
96  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
97  val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
98  val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
99  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
100  val i_mmio_buffer = LazyModule(new TLBuffer)
101
102  val clint_int_node = IntIdentityNode()
103  val debug_int_node = IntIdentityNode()
104  val plic_int_node = IntIdentityNode()
105  val nmi_int_node = IntIdentityNode()
106  val beu_local_int_source = IntSourceNode(IntSourcePortSimple())
107
108  println(s"enableCHI: ${enableCHI}")
109  val l2cache = if (enableL2) {
110    val config = new Config((_, _, _) => {
111      case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
112        hartId = p(XSCoreParamsKey).HartId,
113        FPGAPlatform = debugOpts.FPGAPlatform,
114        hasMbist = hasMbist
115      )
116      case EnableCHI => p(EnableCHI)
117      case CHIIssue => p(CHIIssue)
118      case BankBitsKey => log2Ceil(coreParams.L2NBanks)
119      case MaxHartIdBits => p(MaxHartIdBits)
120      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
121      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
122    })
123    if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
124    else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
125  } else None
126  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
127
128  // =========== Connection ============
129  // l2 to l2_binder, then to memory_port
130  l2cache match {
131    case Some(l2) =>
132      l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu
133      l2 match {
134        case l2: TL2TLCoupledL2 =>
135          memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get
136        case l2: TL2CHICoupledL2 =>
137          l2.managerNode := TLXbar() :=* l2_binder.get
138          l2.mmioNode := mmio_port
139      }
140    case None =>
141      memory_port.get := l1_xbar
142  }
143
144  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
145  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
146  beu.node := TLBuffer.chainNode(1) := mmio_xbar
147  if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) {
148    icachectrl_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
149  }
150  if (SeperateDMBus) {
151    sep_dm_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
152  }
153
154  // filter out in-core addresses before sent to mmio_port
155  // Option[AddressSet] ++ Option[AddressSet] => List[AddressSet]
156  private def cacheAddressSet: Seq[AddressSet] = (icacheParameters.cacheCtrlAddressOpt ++ dcacheParameters.cacheCtrlAddressOpt).toSeq
157  private def mmioFilters = if(SeperateDMBus) (p(DebugModuleKey).get.address +: cacheAddressSet) else cacheAddressSet
158  mmio_port :=
159    TLFilter(TLFilter.mSubtract(mmioFilters)) :=
160    TLBuffer() :=
161    mmio_xbar
162
163  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
164    val io = IO(new Bundle {
165      val beu_errors = Input(chiselTypeOf(beu.module.io.errors))
166      val reset_vector = new Bundle {
167        val fromTile = Input(UInt(PAddrBits.W))
168        val toCore = Output(UInt(PAddrBits.W))
169      }
170      val hartId = new Bundle() {
171        val fromTile = Input(UInt(64.W))
172        val toCore = Output(UInt(64.W))
173      }
174      val msiInfo = new Bundle() {
175        val fromTile = Input(ValidIO(new MsiInfoBundle))
176        val toCore = Output(ValidIO(new MsiInfoBundle))
177      }
178      val cpu_halt = new Bundle() {
179        val fromCore = Input(Bool())
180        val toTile = Output(Bool())
181      }
182      val cpu_critical_error = new Bundle() {
183        val fromCore = Input(Bool())
184        val toTile = Output(Bool())
185      }
186      val hartIsInReset = new Bundle() {
187        val resetInFrontend = Input(Bool())
188        val toTile = Output(Bool())
189      }
190      val traceCoreInterface = new Bundle{
191        val fromCore = Flipped(new TraceCoreInterface)
192        val toTile   = new TraceCoreInterface
193      }
194      val debugTopDown = new Bundle() {
195        val robTrueCommit = Input(UInt(64.W))
196        val robHeadPaddr = Flipped(Valid(UInt(36.W)))
197        val l2MissMatch = Output(Bool())
198      }
199      val l2Miss = Output(Bool())
200      val l3Miss = new Bundle {
201        val fromTile = Input(Bool())
202        val toCore = Output(Bool())
203      }
204      val clintTime = new Bundle {
205        val fromTile = Input(ValidIO(UInt(64.W)))
206        val toCore = Output(ValidIO(UInt(64.W)))
207      }
208      val chi = if (enableCHI) Some(new PortIO) else None
209      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
210      val pfCtrlFromCore = Input(new PrefetchCtrlFromCore)
211      val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
212      val l2_pmp_resp = Flipped(new PMPRespBundle)
213      val l2_hint = ValidIO(new L2ToL1Hint())
214      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
215      val l2_flush_en = Option.when(EnablePowerDown) (Input(Bool()))
216      val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool()))
217      val sramTestIn = new Bundle() {
218        val mbist      = Option.when(hasMbist)(Input(new SramMbistBundle))
219        val mbistReset = Option.when(hasMbist)(Input(new DFTResetSignals()))
220        val sramCtl    = Option.when(hasSramCtl)(Input(UInt(64.W)))
221      }
222      val sramTestOut = new Bundle() {
223        val mbist      = Option.when(hasMbist)(Output(new SramMbistBundle))
224        val mbistReset = Option.when(hasMbist)(Output(new DFTResetSignals()))
225        val sramCtl    = Option.when(hasSramCtl)(Output(UInt(64.W)))
226      }
227      // val reset_core = IO(Output(Reset()))
228    })
229    io.sramTestOut.mbist.zip(io.sramTestIn.mbist).foreach({case(a, b) => a := b})
230    io.sramTestOut.mbistReset.zip(io.sramTestIn.mbistReset).foreach({case(a, b) => a := b})
231    io.sramTestOut.sramCtl.zip(io.sramTestIn.sramCtl).foreach({case(a, b) => a := b})
232
233    val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
234
235    val (beu_int_out, _) = beu_local_int_source.out(0)
236    beu_int_out(0) := beu.module.io.interrupt
237
238    beu.module.io.errors.icache := io.beu_errors.icache
239    beu.module.io.errors.dcache := io.beu_errors.dcache
240    resetDelayN.io.in := io.reset_vector.fromTile
241    io.reset_vector.toCore := resetDelayN.io.out
242    io.hartId.toCore := io.hartId.fromTile
243    io.msiInfo.toCore := io.msiInfo.fromTile
244    io.cpu_halt.toTile := io.cpu_halt.fromCore
245    io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
246    io.l3Miss.toCore := io.l3Miss.fromTile
247    io.clintTime.toCore := io.clintTime.fromTile
248    // trace interface
249    val traceToTile = io.traceCoreInterface.toTile
250    val traceFromCore = io.traceCoreInterface.fromCore
251    traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
252    traceToTile.toEncoder.trap := RegEnable(
253      traceFromCore.toEncoder.trap,
254      traceFromCore.toEncoder.groups(0).valid && Itype.isTrap(traceFromCore.toEncoder.groups(0).bits.itype)
255    )
256    traceToTile.toEncoder.priv := RegEnable(
257      traceFromCore.toEncoder.priv,
258      traceFromCore.toEncoder.groups(0).valid
259    )
260    (0 until TraceGroupNum).foreach{ i =>
261      traceToTile.toEncoder.groups(i).valid := RegNext(traceFromCore.toEncoder.groups(i).valid)
262      traceToTile.toEncoder.groups(i).bits.iretire := RegNext(traceFromCore.toEncoder.groups(i).bits.iretire)
263      traceToTile.toEncoder.groups(i).bits.itype := RegNext(traceFromCore.toEncoder.groups(i).bits.itype)
264      traceToTile.toEncoder.groups(i).bits.ilastsize := RegEnable(
265        traceFromCore.toEncoder.groups(i).bits.ilastsize,
266        traceFromCore.toEncoder.groups(i).valid
267      )
268      traceToTile.toEncoder.groups(i).bits.iaddr := RegEnable(
269        traceFromCore.toEncoder.groups(i).bits.iaddr,
270        traceFromCore.toEncoder.groups(i).valid
271      )
272    }
273
274    dontTouch(io.hartId)
275    dontTouch(io.cpu_halt)
276    dontTouch(io.cpu_critical_error)
277    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
278
279    val hartIsInReset = RegInit(true.B)
280    hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
281    io.hartIsInReset.toTile := hartIsInReset
282
283    if (l2cache.isDefined) {
284      val l2 = l2cache.get.module
285
286      l2.io.pfCtrlFromCore := io.pfCtrlFromCore
287      l2.io.sramTest.mbist.zip(io.sramTestIn.mbist).foreach({ case (a, b) => a := b })
288      l2.io.sramTest.mbistReset.zip(io.sramTestIn.mbistReset).foreach({ case (a, b) => a := b })
289      l2.io.sramTest.sramCtl.zip(io.sramTestIn.sramCtl).foreach({ case (a, b) => a := b })
290      io.l2_hint := l2.io.l2_hint
291      l2.io.debugTopDown.robHeadPaddr := DontCare
292      l2.io.hartId := io.hartId.fromTile
293      l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
294      l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
295      io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
296      io.l2Miss := l2.io.l2Miss
297      io.l2_flush_done.foreach { _ := l2.io.l2FlushDone.getOrElse(false.B) }
298      l2.io.l2Flush.foreach { _ := io.l2_flush_en.getOrElse(false.B) }
299
300      /* l2 tlb */
301      io.l2_tlb_req.req.bits := DontCare
302      io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid
303      io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready
304      io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr
305      io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd
306      io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size
307      io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
308      io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
309      io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
310      io.perfEvents := l2.io_perf
311
312      val allPerfEvents = l2.getPerfEvents
313      if (printEventCoding) {
314        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
315          println("L2 Cache perfEvents Set", name, inc, i)
316        }
317      }
318
319      l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
320      l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
321      l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
322      l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head
323      l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss
324      l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf
325      l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf
326      l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af
327      l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld
328      l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st
329      l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr
330      l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio
331      l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic
332      l2cache.get match {
333        case l2cache: TL2CHICoupledL2 =>
334          val l2 = l2cache.module
335          l2.io_nodeID := io.nodeID.get
336          io.chi.get <> l2.io_chi
337          l2.io_cpu_halt.foreach { _:= io.cpu_halt.fromCore }
338        case l2cache: TL2TLCoupledL2 =>
339      }
340
341      beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
342      beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
343    } else {
344      io.l2_hint := 0.U.asTypeOf(io.l2_hint)
345      io.debugTopDown <> DontCare
346      io.l2Miss := false.B
347
348      io.l2_tlb_req.req.valid := false.B
349      io.l2_tlb_req.req.bits := DontCare
350      io.l2_tlb_req.req_kill := DontCare
351      io.l2_tlb_req.resp.ready := true.B
352      io.perfEvents := DontCare
353
354      beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2)
355    }
356  }
357
358  lazy val module = new Imp(this)
359}
360
361class L2Top()(implicit p: Parameters) extends LazyModule
362  with HasXSParameter
363  with HasSoCParameter {
364
365  override def shouldBeInlined: Boolean = false
366
367  val inner = LazyModule(new L2TopInlined())
368
369  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
370    val io = IO(inner.module.io.cloneType)
371    val reset_core = IO(Output(Reset()))
372    io <> inner.module.io
373
374    if (debugOpts.ResetGen) {
375      ResetGen(ResetGenNode(Seq(
376        CellNode(reset_core),
377        ModuleNode(inner.module)
378      )), reset, sim = false, io.sramTestIn.mbistReset)
379    } else {
380      reset_core := DontCare
381    }
382  }
383
384  lazy val module = new Imp(this)
385}
386