1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# enable or disable dfx manually 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --dfx true 83else 84ifeq ($(DFX),0) 85COMMON_EXTRA_ARGS += --dfx false 86endif 87endif 88 89# enable or disable sram ctl maunally 90ifeq ($(SRAM_WITH_CTL),1) 91COMMON_EXTRA_ARGS += --sram-with-ctl 92endif 93 94# enable non-secure access or not 95# CHI requests are secure as default by now 96ifeq ($(ENABLE_NS),1) 97COMMON_EXTRA_ARGS += --enable-ns 98endif 99 100# L2 cache size in KB 101ifneq ($(L2_CACHE_SIZE),) 102COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 103endif 104 105# L3 cache size in KB 106ifneq ($(L3_CACHE_SIZE),) 107COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 108endif 109 110# configuration from yaml file 111ifneq ($(YAML_CONFIG),) 112COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 113endif 114 115# hart id bits 116ifneq ($(HART_ID_BITS),) 117COMMON_EXTRA_ARGS += --hartidbits $(HART_ID_BITS) 118endif 119 120# public args sumup 121RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 122DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 123override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 124 125# co-simulation with DRAMsim3 126ifeq ($(WITH_DRAMSIM3),1) 127ifndef DRAMSIM3_HOME 128$(error DRAMSIM3_HOME is not set) 129endif 130override SIM_ARGS += --with-dramsim3 131endif 132 133# run emu with chisel-db 134ifeq ($(WITH_CHISELDB),1) 135override SIM_ARGS += --with-chiseldb 136endif 137 138# run emu with chisel-db 139ifeq ($(WITH_ROLLINGDB),1) 140override SIM_ARGS += --with-rollingdb 141endif 142 143# enable ResetGen 144ifeq ($(WITH_RESETGEN),1) 145override SIM_ARGS += --reset-gen 146endif 147 148# run with disable all perf 149ifeq ($(DISABLE_PERF),1) 150override SIM_ARGS += --disable-perf 151endif 152 153# run with disable all db 154ifeq ($(DISABLE_ALWAYSDB),1) 155override SIM_ARGS += --disable-alwaysdb 156endif 157 158# dynamic switch CONSTANTIN 159ifeq ($(WITH_CONSTANTIN),1) 160override SIM_ARGS += --with-constantin 161endif 162 163# emu for the release version 164RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 165DEBUG_ARGS += --enable-difftest 166override PLDM_ARGS += --enable-difftest 167ifeq ($(RELEASE),1) 168override SIM_ARGS += $(RELEASE_ARGS) 169else ifeq ($(PLDM),1) 170override SIM_ARGS += $(PLDM_ARGS) 171else 172override SIM_ARGS += $(DEBUG_ARGS) 173endif 174 175# use RELEASE_ARGS for TopMain by default 176ifeq ($(PLDM), 1) 177TOPMAIN_ARGS += $(PLDM_ARGS) 178else 179TOPMAIN_ARGS += $(RELEASE_ARGS) 180endif 181 182TIMELOG = $(BUILD_DIR)/time.log 183TIME_CMD = time -avp -o $(TIMELOG) 184 185ifeq ($(PLDM),1) 186SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 187SED_ENDIF = `endif // not def SYNTHESIS 188endif 189 190.DEFAULT_GOAL = verilog 191 192help: 193 mill -i xiangshan.runMain $(FPGATOP) --help 194 195version: 196 mill -i xiangshan.runMain $(FPGATOP) --version 197 198jar: 199 mill -i xiangshan.assembly 200 201test-jar: 202 mill -i xiangshan.test.assembly 203 204comp: 205 mill -i xiangshan.compile 206 mill -i xiangshan.test.compile 207 208$(TOP_V): $(SCALA_FILE) 209 mkdir -p $(@D) 210 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 211 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 212 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 213ifeq ($(CHISEL_TARGET),systemverilog) 214 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 215 @git log -n 1 >> .__head__ 216 @git diff >> .__diff__ 217 @sed -i 's/^/\/\// ' .__head__ 218 @sed -i 's/^/\/\//' .__diff__ 219 @cat .__head__ .__diff__ $@ > .__out__ 220 @mv .__out__ $@ 221 @rm .__head__ .__diff__ 222endif 223 224verilog: $(TOP_V) 225 226$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 227 mkdir -p $(@D) 228 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 229 @date -R | tee -a $(TIMELOG) 230 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 231 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 232 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 233ifeq ($(CHISEL_TARGET),systemverilog) 234 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 235 @git log -n 1 >> .__head__ 236 @git diff >> .__diff__ 237 @sed -i 's/^/\/\// ' .__head__ 238 @sed -i 's/^/\/\//' .__diff__ 239 @cat .__head__ .__diff__ $@ > .__out__ 240 @mv .__out__ $@ 241 @rm .__head__ .__diff__ 242ifeq ($(PLDM),1) 243 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 244 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 245else 246ifeq ($(ENABLE_XPROP),1) 247 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 248else 249 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 250endif 251endif 252 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 253endif 254 255sim-verilog: $(SIM_TOP_V) 256 257clean: 258 $(MAKE) -C ./difftest clean 259 rm -rf $(BUILD_DIR) 260 261init: 262 git submodule update --init 263 cd rocket-chip && git submodule update --init cde hardfloat 264 cd openLLC && git submodule update --init openNCB 265 266bump: 267 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 268 269bsp: 270 mill -i mill.bsp.BSP/install 271 272idea: 273 mill -i mill.idea.GenIdea/idea 274 275check-format: 276 mill xiangshan.checkFormat 277 278reformat: 279 mill xiangshan.reformat 280 281# verilator simulation 282emu: sim-verilog 283 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 284 285emu-run: emu 286 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 287 288# vcs simulation 289simv: sim-verilog 290 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 291 292simv-run: 293 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 294 295# palladium simulation 296pldm-build: sim-verilog 297 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 298 299pldm-run: 300 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 301 302pldm-debug: 303 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 304 305include Makefile.test 306 307include src/main/scala/device/standalone/standalone_device.mk 308 309.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 310