1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import system.CVMParamskey 25import xiangshan.backend.datapath.RdConfig._ 26import xiangshan.backend.datapath.WbConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasBitmapCheck: Boolean = false, 65 HasBitmapCheckDefault: Boolean = false, 66 HasMExtension: Boolean = true, 67 HasCExtension: Boolean = true, 68 HasHExtension: Boolean = true, 69 HasDiv: Boolean = true, 70 HasICache: Boolean = true, 71 HasDCache: Boolean = true, 72 AddrBits: Int = 64, 73 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 74 VAddrBitsSv39: Int = 39, 75 GPAddrBitsSv39x4: Int = 41, 76 VAddrBitsSv48: Int = 48, 77 GPAddrBitsSv48x4: Int = 50, 78 HasFPU: Boolean = true, 79 HasVPU: Boolean = true, 80 HasCustomCSRCacheOp: Boolean = true, 81 FetchWidth: Int = 8, 82 AsidLength: Int = 16, 83 VmidLength: Int = 14, 84 EnableBPU: Boolean = true, 85 EnableBPD: Boolean = true, 86 EnableRAS: Boolean = true, 87 EnableLB: Boolean = false, 88 EnableLoop: Boolean = true, 89 EnableSC: Boolean = true, 90 EnbaleTlbDebug: Boolean = false, 91 EnableClockGate: Boolean = true, 92 EnableJal: Boolean = false, 93 EnableFauFTB: Boolean = true, 94 EnableSv48: Boolean = true, 95 UbtbGHRLength: Int = 4, 96 // HistoryLength: Int = 512, 97 EnableGHistDiff: Boolean = true, 98 EnableCommitGHistDiff: Boolean = true, 99 UbtbSize: Int = 256, 100 FtbSize: Int = 2048, 101 FtbWays: Int = 4, 102 FtbTagLength: Int = 20, 103 RasSize: Int = 16, 104 RasSpecSize: Int = 32, 105 RasCtrSize: Int = 3, 106 CacheLineSize: Int = 512, 107 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 108 // Sets Hist Tag 109 Seq(( 4096, 8, 8), 110 ( 4096, 13, 8), 111 ( 4096, 32, 8), 112 ( 4096, 119, 8)), 113 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 114 // Sets Hist Tag 115 Seq(( 256, 4, 9), 116 ( 256, 8, 9), 117 ( 512, 13, 9), 118 ( 512, 16, 9), 119 ( 512, 32, 9)), 120 SCNRows: Int = 512, 121 SCNTables: Int = 4, 122 SCCtrBits: Int = 6, 123 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 124 numBr: Int = 2, 125 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 126 (resp_in: BranchPredictionResp, p: Parameters) => { 127 val ftb = Module(new FTB()(p)) 128 val uftb = Module(new FauFTB()(p)) 129 val tage = Module(new Tage_SC()(p)) 130 val ras = Module(new RAS()(p)) 131 val ittage = Module(new ITTage()(p)) 132 val preds = Seq(uftb, tage, ftb, ittage, ras) 133 preds.map(_.io := DontCare) 134 135 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 136 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 137 138 uftb.io.in.bits.resp_in(0) := resp_in 139 tage.io.in.bits.resp_in(0) := uftb.io.out 140 ftb.io.in.bits.resp_in(0) := tage.io.out 141 ittage.io.in.bits.resp_in(0) := ftb.io.out 142 ras.io.in.bits.resp_in(0) := ittage.io.out 143 144 (preds, ras.io.out) 145 }, 146 ICacheForceMetaECCError: Boolean = false, 147 ICacheForceDataECCError: Boolean = false, 148 IBufSize: Int = 48, 149 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 150 DecodeWidth: Int = 6, 151 RenameWidth: Int = 6, 152 CommitWidth: Int = 8, 153 RobCommitWidth: Int = 8, 154 RabCommitWidth: Int = 6, 155 MaxUopSize: Int = 65, 156 EnableRenameSnapshot: Boolean = true, 157 RenameSnapshotNum: Int = 4, 158 FtqSize: Int = 64, 159 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 160 IntLogicRegs: Int = 32, 161 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 162 VecLogicRegs: Int = 32 + 15, // 15: tmp 163 V0LogicRegs: Int = 1, // V0 164 VlLogicRegs: Int = 1, // Vl 165 V0_IDX: Int = 0, 166 Vl_IDX: Int = 0, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 4, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 56, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 intPreg: PregParams = IntPregParams( 185 numEntries = 224, 186 numRead = None, 187 numWrite = None, 188 ), 189 fpPreg: PregParams = FpPregParams( 190 numEntries = 192, 191 numRead = None, 192 numWrite = None, 193 ), 194 vfPreg: VfPregParams = VfPregParams( 195 numEntries = 128, 196 numRead = None, 197 numWrite = None, 198 ), 199 v0Preg: V0PregParams = V0PregParams( 200 numEntries = 22, 201 numRead = None, 202 numWrite = None, 203 ), 204 vlPreg: VlPregParams = VlPregParams( 205 numEntries = 32, 206 numRead = None, 207 numWrite = None, 208 ), 209 IntRegCacheSize: Int = 16, 210 MemRegCacheSize: Int = 12, 211 intSchdVlWbPort: Int = 0, 212 vfSchdVlWbPort: Int = 1, 213 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 214 IfuRedirectNum: Int = 1, 215 LoadPipelineWidth: Int = 3, 216 StorePipelineWidth: Int = 2, 217 VecLoadPipelineWidth: Int = 2, 218 VecStorePipelineWidth: Int = 2, 219 VecMemSrcInWidth: Int = 2, 220 VecMemInstWbWidth: Int = 1, 221 VecMemDispatchWidth: Int = 1, 222 VecMemDispatchMaxNumber: Int = 16, 223 VecMemUnitStrideMaxFlowNum: Int = 2, 224 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 225 StoreBufferSize: Int = 16, 226 StoreBufferThreshold: Int = 7, 227 EnsbufferWidth: Int = 2, 228 LoadDependencyWidth: Int = 2, 229 // ============ VLSU ============ 230 VlMergeBufferSize: Int = 16, 231 VsMergeBufferSize: Int = 16, 232 UopWritebackWidth: Int = 2, 233 VLUopWritebackWidth: Int = 2, 234 VSUopWritebackWidth: Int = 1, 235 VSegmentBufferSize: Int = 8, 236 VFOFBufferSize: Int = 8, 237 VLFOFWritebackWidth: Int = 1, 238 // ============================== 239 UncacheBufferSize: Int = 4, 240 EnableLoadToLoadForward: Boolean = false, 241 EnableFastForward: Boolean = true, 242 EnableLdVioCheckAfterReset: Boolean = true, 243 EnableSoftPrefetchAfterReset: Boolean = true, 244 EnableCacheErrorAfterReset: Boolean = true, 245 EnableAccurateLoadError: Boolean = true, 246 EnableUncacheWriteOutstanding: Boolean = false, 247 EnableHardwareStoreMisalign: Boolean = true, 248 EnableHardwareLoadMisalign: Boolean = true, 249 EnableStorePrefetchAtIssue: Boolean = false, 250 EnableStorePrefetchAtCommit: Boolean = false, 251 EnableAtCommitMissTrigger: Boolean = true, 252 EnableStorePrefetchSMS: Boolean = false, 253 EnableStorePrefetchSPB: Boolean = false, 254 HasCMO: Boolean = true, 255 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 256 MMUVmidLen: Int = 14, 257 ReSelectLen: Int = 7, // load replay queue replay select counter len 258 iwpuParameters: WPUParameters = WPUParameters( 259 enWPU = false, 260 algoName = "mmru", 261 isICache = true, 262 ), 263 dwpuParameters: WPUParameters = WPUParameters( 264 enWPU = false, 265 algoName = "mmru", 266 enCfPred = false, 267 isICache = false, 268 ), 269 itlbParameters: TLBParameters = TLBParameters( 270 name = "itlb", 271 fetchi = true, 272 useDmode = false, 273 NWays = 48, 274 ), 275 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 276 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 277 ldtlbParameters: TLBParameters = TLBParameters( 278 name = "ldtlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = false, 284 lgMaxSize = 4 285 ), 286 sttlbParameters: TLBParameters = TLBParameters( 287 name = "sttlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = false, 293 lgMaxSize = 4 294 ), 295 hytlbParameters: TLBParameters = TLBParameters( 296 name = "hytlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = false, 302 lgMaxSize = 4 303 ), 304 pftlbParameters: TLBParameters = TLBParameters( 305 name = "pftlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = false, 311 lgMaxSize = 4 312 ), 313 l2ToL1tlbParameters: TLBParameters = TLBParameters( 314 name = "l2tlb", 315 NWays = 48, 316 outReplace = false, 317 partialStaticPMP = true, 318 outsideRecvFlush = true, 319 saveLevel = false 320 ), 321 refillBothTlb: Boolean = false, 322 btlbParameters: TLBParameters = TLBParameters( 323 name = "btlb", 324 NWays = 48, 325 ), 326 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 327 NumPerfCounters: Int = 16, 328 icacheParameters: ICacheParameters = ICacheParameters( 329 tagECC = Some("parity"), 330 dataECC = Some("parity"), 331 replacer = Some("setplru"), 332 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 333 ), 334 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 replacer = Some("setplru"), 338 nMissEntries = 16, 339 nProbeEntries = 8, 340 nReleaseEntries = 18, 341 nMaxPrefetchEntry = 6, 342 enableTagEcc = true, 343 enableDataEcc = true, 344 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 345 )), 346 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 347 name = "l2", 348 ways = 8, 349 sets = 1024, // default 512KB L2 350 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 351 coupledL2.prefetch.TPParameters()), 352 )), 353 L2NBanks: Int = 1, 354 usePTWRepeater: Boolean = false, 355 softTLB: Boolean = false, // dpi-c l1tlb debug only 356 softPTW: Boolean = false, // dpi-c l2tlb debug only 357 softPTWDelay: Int = 1, 358 hasMbist: Boolean = false, 359 hasSramCtl: Boolean = false, 360){ 361 def ISABase = "rv64i" 362 def ISAExtensions = Seq( 363 // single letter extensions, in canonical order 364 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 365 // multi-letter extensions, sorted alphanumerically 366 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 367 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 368 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 369 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 370 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 371 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 372 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 373 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 374 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 375 ) 376 377 def vlWidth = log2Up(VLEN) + 1 378 379 /** 380 * the minimum element length of vector elements 381 */ 382 val minVecElen: Int = 8 383 384 /** 385 * the maximum number of elements in vector register 386 */ 387 val maxElemPerVreg: Int = VLEN / minVecElen 388 389 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 390 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 391 392 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 393 val RegCacheIdxWidth = log2Up(RegCacheSize) 394 395 val intSchdParams = { 396 implicit val schdType: SchedulerType = IntScheduler() 397 SchdBlockParams(Seq( 398 IssueBlockParams(Seq( 399 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 400 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 401 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 402 IssueBlockParams(Seq( 403 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 404 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 405 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 406 IssueBlockParams(Seq( 407 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 408 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 412 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 ), 415 numPregs = intPreg.numEntries, 416 numDeqOutside = 0, 417 schdType = schdType, 418 rfDataWidth = intPreg.dataCfg.dataWidth, 419 ) 420 } 421 422 val fpSchdParams = { 423 implicit val schdType: SchedulerType = FpScheduler() 424 SchdBlockParams(Seq( 425 IssueBlockParams(Seq( 426 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 427 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 428 ), numEntries = 18, numEnq = 2, numComp = 14), 429 IssueBlockParams(Seq( 430 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 431 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 432 ), numEntries = 18, numEnq = 2, numComp = 14), 433 IssueBlockParams(Seq( 434 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 435 ), numEntries = 18, numEnq = 2, numComp = 14), 436 ), 437 numPregs = fpPreg.numEntries, 438 numDeqOutside = 0, 439 schdType = schdType, 440 rfDataWidth = fpPreg.dataCfg.dataWidth, 441 ) 442 } 443 444 val vfSchdParams = { 445 implicit val schdType: SchedulerType = VfScheduler() 446 SchdBlockParams(Seq( 447 IssueBlockParams(Seq( 448 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 449 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 450 ), numEntries = 16, numEnq = 2, numComp = 12), 451 IssueBlockParams(Seq( 452 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 453 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 454 ), numEntries = 16, numEnq = 2, numComp = 12), 455 IssueBlockParams(Seq( 456 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 457 ), numEntries = 10, numEnq = 2, numComp = 6), 458 ), 459 numPregs = vfPreg.numEntries, 460 numDeqOutside = 0, 461 schdType = schdType, 462 rfDataWidth = vfPreg.dataCfg.dataWidth, 463 ) 464 } 465 466 val memSchdParams = { 467 implicit val schdType: SchedulerType = MemScheduler() 468 val rfDataWidth = 64 469 470 SchdBlockParams(Seq( 471 IssueBlockParams(Seq( 472 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 473 ), numEntries = 16, numEnq = 2, numComp = 12), 474 IssueBlockParams(Seq( 475 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 476 ), numEntries = 16, numEnq = 2, numComp = 12), 477 IssueBlockParams(Seq( 478 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 479 ), numEntries = 16, numEnq = 2, numComp = 12), 480 IssueBlockParams(Seq( 481 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 482 ), numEntries = 16, numEnq = 2, numComp = 12), 483 IssueBlockParams(Seq( 484 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 485 ), numEntries = 16, numEnq = 2, numComp = 12), 486 IssueBlockParams(Seq( 487 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 488 ), numEntries = 16, numEnq = 2, numComp = 12), 489 IssueBlockParams(Seq( 490 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 491 ), numEntries = 16, numEnq = 2, numComp = 12), 492 IssueBlockParams(Seq( 493 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 494 ), numEntries = 16, numEnq = 2, numComp = 12), 495 IssueBlockParams(Seq( 496 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 497 ), numEntries = 16, numEnq = 2, numComp = 12), 498 ), 499 numPregs = intPreg.numEntries max vfPreg.numEntries, 500 numDeqOutside = 0, 501 schdType = schdType, 502 rfDataWidth = rfDataWidth, 503 ) 504 } 505 506 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 507 508 def iqWakeUpParams = { 509 Seq( 510 WakeUpConfig( 511 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 512 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 513 ), 514 // TODO: add load -> fp slow wakeup 515 WakeUpConfig( 516 Seq("FEX0", "FEX2", "FEX4") -> 517 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 518 ), 519 ).flatten 520 } 521 522 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 523 524 val backendParams: BackendParams = backend.BackendParams( 525 Map( 526 IntScheduler() -> intSchdParams, 527 FpScheduler() -> fpSchdParams, 528 VfScheduler() -> vfSchdParams, 529 MemScheduler() -> memSchdParams, 530 ), 531 Seq( 532 intPreg, 533 fpPreg, 534 vfPreg, 535 v0Preg, 536 vlPreg, 537 fakeIntPreg 538 ), 539 iqWakeUpParams, 540 ) 541 542 // Parameters for trace extension. 543 // Trace parameters is useful for XSTOP. 544 val traceParams: TraceParams = new TraceParams( 545 TraceGroupNum = 3, 546 IaddrWidth = GPAddrBitsSv48x4, 547 PrivWidth = 3, 548 ItypeWidth = 4, 549 IlastsizeWidth = 1, 550 ) 551} 552 553case object DebugOptionsKey extends Field[DebugOptions] 554 555case class DebugOptions 556( 557 FPGAPlatform: Boolean = false, 558 ResetGen: Boolean = false, 559 EnableDifftest: Boolean = false, 560 AlwaysBasicDiff: Boolean = true, 561 EnableDebug: Boolean = false, 562 EnablePerfDebug: Boolean = true, 563 PerfLevel: String = "VERBOSE", 564 UseDRAMSim: Boolean = false, 565 EnableConstantin: Boolean = false, 566 EnableChiselDB: Boolean = false, 567 AlwaysBasicDB: Boolean = true, 568 EnableRollingDB: Boolean = false 569) 570 571trait HasXSParameter { 572 573 implicit val p: Parameters 574 575 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 576 def PmemRanges = p(SoCParamsKey).PmemRanges 577 def KeyIDBits = p(CVMParamskey).KeyIDBits 578 final val PageOffsetWidth = 12 579 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 580 581 def coreParams = p(XSCoreParamsKey) 582 def env = p(DebugOptionsKey) 583 584 def ISABase = coreParams.ISABase 585 def ISAExtensions = coreParams.ISAExtensions 586 def XLEN = coreParams.XLEN 587 def VLEN = coreParams.VLEN 588 def ELEN = coreParams.ELEN 589 def HSXLEN = coreParams.HSXLEN 590 val minFLen = 32 591 val fLen = 64 592 def hartIdLen = p(MaxHartIdBits) 593 val xLen = XLEN 594 595 def HasBitmapCheck = coreParams.HasBitmapCheck 596 def HasBitmapCheckDefault = coreParams.HasBitmapCheckDefault 597 def HasMExtension = coreParams.HasMExtension 598 def HasCExtension = coreParams.HasCExtension 599 def HasHExtension = coreParams.HasHExtension 600 def EnableSv48 = coreParams.EnableSv48 601 def HasDiv = coreParams.HasDiv 602 def HasIcache = coreParams.HasICache 603 def HasDcache = coreParams.HasDCache 604 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 605 def PAddrBitsMax = coreParams.PAddrBitsMax 606 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 607 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 608 def GPAddrBits = { 609 if (EnableSv48) 610 coreParams.GPAddrBitsSv48x4 611 else 612 coreParams.GPAddrBitsSv39x4 613 } 614 def VAddrBits = { 615 if (HasHExtension) { 616 if (EnableSv48) 617 coreParams.GPAddrBitsSv48x4 618 else 619 coreParams.GPAddrBitsSv39x4 620 } else { 621 if (EnableSv48) 622 coreParams.VAddrBitsSv48 623 else 624 coreParams.VAddrBitsSv39 625 } 626 } // VAddrBits is Virtual Memory addr bits 627 628 def VAddrMaxBits = { 629 if(EnableSv48) { 630 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 631 } else { 632 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 633 } 634 } 635 636 def AsidLength = coreParams.AsidLength 637 def VmidLength = coreParams.VmidLength 638 def ReSelectLen = coreParams.ReSelectLen 639 def AddrBytes = AddrBits / 8 // unused 640 def DataBits = XLEN 641 def DataBytes = DataBits / 8 642 def QuadWordBits = DataBits * 2 643 def QuadWordBytes = QuadWordBits / 8 644 def VDataBytes = VLEN / 8 645 def HasFPU = coreParams.HasFPU 646 def HasVPU = coreParams.HasVPU 647 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 648 def FetchWidth = coreParams.FetchWidth 649 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 650 def EnableBPU = coreParams.EnableBPU 651 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 652 def EnableRAS = coreParams.EnableRAS 653 def EnableLB = coreParams.EnableLB 654 def EnableLoop = coreParams.EnableLoop 655 def EnableSC = coreParams.EnableSC 656 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 657 def HistoryLength = coreParams.HistoryLength 658 def EnableGHistDiff = coreParams.EnableGHistDiff 659 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 660 def EnableClockGate = coreParams.EnableClockGate 661 def UbtbGHRLength = coreParams.UbtbGHRLength 662 def UbtbSize = coreParams.UbtbSize 663 def EnableFauFTB = coreParams.EnableFauFTB 664 def FtbSize = coreParams.FtbSize 665 def FtbWays = coreParams.FtbWays 666 def FtbTagLength = coreParams.FtbTagLength 667 def RasSize = coreParams.RasSize 668 def RasSpecSize = coreParams.RasSpecSize 669 def RasCtrSize = coreParams.RasCtrSize 670 671 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 672 coreParams.branchPredictor(resp_in, p) 673 } 674 def numBr = coreParams.numBr 675 def TageTableInfos = coreParams.TageTableInfos 676 def TageBanks = coreParams.numBr 677 def SCNRows = coreParams.SCNRows 678 def SCCtrBits = coreParams.SCCtrBits 679 def SCHistLens = coreParams.SCHistLens 680 def SCNTables = coreParams.SCNTables 681 682 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 683 case ((n, cb), h) => (n, cb, h) 684 } 685 def ITTageTableInfos = coreParams.ITTageTableInfos 686 type FoldedHistoryInfo = Tuple2[Int, Int] 687 def foldedGHistInfos = 688 (TageTableInfos.map{ case (nRows, h, t) => 689 if (h > 0) 690 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 691 else 692 Set[FoldedHistoryInfo]() 693 }.reduce(_++_).toSet ++ 694 SCTableInfos.map{ case (nRows, _, h) => 695 if (h > 0) 696 Set((h, min(log2Ceil(nRows/TageBanks), h))) 697 else 698 Set[FoldedHistoryInfo]() 699 }.reduce(_++_).toSet ++ 700 ITTageTableInfos.map{ case (nRows, h, t) => 701 if (h > 0) 702 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 703 else 704 Set[FoldedHistoryInfo]() 705 }.reduce(_++_) ++ 706 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 707 ).toList 708 709 710 711 def CacheLineSize = coreParams.CacheLineSize 712 def CacheLineHalfWord = CacheLineSize / 16 713 def ExtHistoryLength = HistoryLength + 64 714 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 715 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 716 def IBufSize = coreParams.IBufSize 717 def IBufNBank = coreParams.IBufNBank 718 def backendParams: BackendParams = coreParams.backendParams 719 def DecodeWidth = coreParams.DecodeWidth 720 def RenameWidth = coreParams.RenameWidth 721 def CommitWidth = coreParams.CommitWidth 722 def RobCommitWidth = coreParams.RobCommitWidth 723 def RabCommitWidth = coreParams.RabCommitWidth 724 def MaxUopSize = coreParams.MaxUopSize 725 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 726 def RenameSnapshotNum = coreParams.RenameSnapshotNum 727 def FtqSize = coreParams.FtqSize 728 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 729 def IntLogicRegs = coreParams.IntLogicRegs 730 def FpLogicRegs = coreParams.FpLogicRegs 731 def VecLogicRegs = coreParams.VecLogicRegs 732 def V0LogicRegs = coreParams.V0LogicRegs 733 def VlLogicRegs = coreParams.VlLogicRegs 734 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 735 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 736 def V0_IDX = coreParams.V0_IDX 737 def Vl_IDX = coreParams.Vl_IDX 738 def IntPhyRegs = coreParams.intPreg.numEntries 739 def FpPhyRegs = coreParams.fpPreg.numEntries 740 def VfPhyRegs = coreParams.vfPreg.numEntries 741 def V0PhyRegs = coreParams.v0Preg.numEntries 742 def VlPhyRegs = coreParams.vlPreg.numEntries 743 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 744 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 745 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 746 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 747 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 748 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 749 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 750 def RobSize = coreParams.RobSize 751 def RabSize = coreParams.RabSize 752 def VTypeBufferSize = coreParams.VTypeBufferSize 753 def IntRegCacheSize = coreParams.IntRegCacheSize 754 def MemRegCacheSize = coreParams.MemRegCacheSize 755 def RegCacheSize = coreParams.RegCacheSize 756 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 757 /** 758 * the minimum element length of vector elements 759 */ 760 def minVecElen: Int = coreParams.minVecElen 761 762 /** 763 * the maximum number of elements in vector register 764 */ 765 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 766 767 def IntRefCounterWidth = log2Ceil(RobSize) 768 def LSQEnqWidth = RenameWidth 769 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 770 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 771 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 772 def LoadQueueRARSize = coreParams.LoadQueueRARSize 773 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 774 def RollbackGroupSize = coreParams.RollbackGroupSize 775 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 776 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 777 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 778 def StoreQueueSize = coreParams.StoreQueueSize 779 def StoreQueueForceWriteSbufferUpper = coreParams.StoreQueueSize - 4 780 def StoreQueueForceWriteSbufferLower = StoreQueueForceWriteSbufferUpper - 5 781 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 782 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 783 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 784 def VlsQueueSize = coreParams.VlsQueueSize 785 786 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 787 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 788 789 def NumRedirect = backendParams.numRedirect 790 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 791 def FtqRedirectAheadNum = NumRedirect 792 def IfuRedirectNum = coreParams.IfuRedirectNum 793 def LoadPipelineWidth = coreParams.LoadPipelineWidth 794 def StorePipelineWidth = coreParams.StorePipelineWidth 795 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 796 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 797 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 798 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 799 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 800 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 801 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 802 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 803 def StoreBufferSize = coreParams.StoreBufferSize 804 def StoreBufferThreshold = coreParams.StoreBufferThreshold 805 def EnsbufferWidth = coreParams.EnsbufferWidth 806 def LoadDependencyWidth = coreParams.LoadDependencyWidth 807 def VlMergeBufferSize = coreParams.VlMergeBufferSize 808 def VsMergeBufferSize = coreParams.VsMergeBufferSize 809 def UopWritebackWidth = coreParams.UopWritebackWidth 810 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 811 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 812 def VSegmentBufferSize = coreParams.VSegmentBufferSize 813 def VFOFBufferSize = coreParams.VFOFBufferSize 814 def UncacheBufferSize = coreParams.UncacheBufferSize 815 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 816 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 817 def EnableFastForward = coreParams.EnableFastForward 818 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 819 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 820 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 821 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 822 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 823 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 824 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 825 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 826 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 827 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 828 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 829 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 830 def HasCMO = coreParams.HasCMO && p(EnableCHI) 831 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 832 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 833 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 834 def asidLen = coreParams.MMUAsidLen 835 def vmidLen = coreParams.MMUVmidLen 836 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 837 def refillBothTlb = coreParams.refillBothTlb 838 def iwpuParam = coreParams.iwpuParameters 839 def dwpuParam = coreParams.dwpuParameters 840 def itlbParams = coreParams.itlbParameters 841 def ldtlbParams = coreParams.ldtlbParameters 842 def sttlbParams = coreParams.sttlbParameters 843 def hytlbParams = coreParams.hytlbParameters 844 def pftlbParams = coreParams.pftlbParameters 845 def l2ToL1Params = coreParams.l2ToL1tlbParameters 846 def btlbParams = coreParams.btlbParameters 847 def l2tlbParams = coreParams.l2tlbParameters 848 def NumPerfCounters = coreParams.NumPerfCounters 849 850 def instBytes = if (HasCExtension) 2 else 4 851 def instOffsetBits = log2Ceil(instBytes) 852 853 def icacheParameters = coreParams.icacheParameters 854 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 855 856 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 857 // for constrained LR/SC loop 858 def LRSCCycles = 64 859 // for lr storm 860 def LRSCBackOff = 8 861 862 // cache hierarchy configurations 863 def l1BusDataWidth = 256 864 865 // load violation predict 866 def ResetTimeMax2Pow = 20 //1078576 867 def ResetTimeMin2Pow = 10 //1024 868 // wait table parameters 869 def WaitTableSize = 1024 870 def MemPredPCWidth = log2Up(WaitTableSize) 871 def LWTUse2BitCounter = true 872 // store set parameters 873 def SSITSize = WaitTableSize 874 def LFSTSize = 32 875 def SSIDWidth = log2Up(LFSTSize) 876 def LFSTWidth = 4 877 def StoreSetEnable = true // LWT will be disabled if SS is enabled 878 def LFSTEnable = true 879 880 def PCntIncrStep: Int = 6 881 def numPCntHc: Int = 12 882 def numPCntPtw: Int = 19 883 884 def numCSRPCntFrontend = 8 885 def numCSRPCntCtrl = 8 886 def numCSRPCntLsu = 8 887 def numCSRPCntHc = 5 888 def printEventCoding = true 889 def printCriticalError = false 890 def maxCommitStuck = pow(2, 21).toInt 891 892 // Vector load exception 893 def maxMergeNumPerCycle = 4 894 895 // Parameters for Sdtrig extension 896 protected def TriggerNum = 4 897 protected def TriggerChainMaxLength = 2 898 899 // Parameters for Trace extension 900 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 901 def CauseWidth = XLEN 902 def TvalWidth = coreParams.traceParams.IaddrWidth 903 def PrivWidth = coreParams.traceParams.PrivWidth 904 def IaddrWidth = coreParams.traceParams.IaddrWidth 905 def ItypeWidth = coreParams.traceParams.ItypeWidth 906 def IretireWidthInPipe = log2Up(RenameWidth * 2) 907 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 908 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 909 910 def hasMbist = coreParams.hasMbist 911 def hasSramCtl = coreParams.hasSramCtl 912 def hasSramTest = hasMbist || hasSramCtl 913} 914