1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# enable or disable dfx manually 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --dfx true 83else 84ifeq ($(DFX),0) 85COMMON_EXTRA_ARGS += --dfx false 86endif 87endif 88 89# enable or disable sram ctl maunally 90ifeq ($(SRAM_WITH_CTL),1) 91COMMON_EXTRA_ARGS += --sram-with-ctl 92endif 93 94# L2 cache size in KB 95ifneq ($(L2_CACHE_SIZE),) 96COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 97endif 98 99# L3 cache size in KB 100ifneq ($(L3_CACHE_SIZE),) 101COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 102endif 103 104# seperate bus for DebugModule 105ifeq ($(SEPERATE_DM_BUS),1) 106COMMON_EXTRA_ARGS += --seperate-dm-bus 107endif 108 109# configuration from yaml file 110ifneq ($(YAML_CONFIG),) 111COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 112endif 113 114# hart id bits 115ifneq ($(HART_ID_BITS),) 116COMMON_EXTRA_ARGS += --hartidbits $(HART_ID_BITS) 117endif 118 119# public args sumup 120RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 121DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 122override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 123 124# co-simulation with DRAMsim3 125ifeq ($(WITH_DRAMSIM3),1) 126ifndef DRAMSIM3_HOME 127$(error DRAMSIM3_HOME is not set) 128endif 129override SIM_ARGS += --with-dramsim3 130endif 131 132# run emu with chisel-db 133ifeq ($(WITH_CHISELDB),1) 134override SIM_ARGS += --with-chiseldb 135endif 136 137# run emu with chisel-db 138ifeq ($(WITH_ROLLINGDB),1) 139override SIM_ARGS += --with-rollingdb 140endif 141 142# enable ResetGen 143ifeq ($(WITH_RESETGEN),1) 144override SIM_ARGS += --reset-gen 145endif 146 147# run with disable all perf 148ifeq ($(DISABLE_PERF),1) 149override SIM_ARGS += --disable-perf 150endif 151 152# run with disable all db 153ifeq ($(DISABLE_ALWAYSDB),1) 154override SIM_ARGS += --disable-alwaysdb 155endif 156 157# dynamic switch CONSTANTIN 158ifeq ($(WITH_CONSTANTIN),1) 159override SIM_ARGS += --with-constantin 160endif 161 162# emu for the release version 163RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 164DEBUG_ARGS += --enable-difftest 165override PLDM_ARGS += --enable-difftest 166ifeq ($(RELEASE),1) 167override SIM_ARGS += $(RELEASE_ARGS) 168else ifeq ($(PLDM),1) 169override SIM_ARGS += $(PLDM_ARGS) 170else 171override SIM_ARGS += $(DEBUG_ARGS) 172endif 173 174# use RELEASE_ARGS for TopMain by default 175ifeq ($(PLDM), 1) 176TOPMAIN_ARGS += $(PLDM_ARGS) 177else 178TOPMAIN_ARGS += $(RELEASE_ARGS) 179endif 180 181TIMELOG = $(BUILD_DIR)/time.log 182TIME_CMD = time -avp -o $(TIMELOG) 183 184ifeq ($(PLDM),1) 185SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 186SED_ENDIF = `endif // not def SYNTHESIS 187endif 188 189.DEFAULT_GOAL = verilog 190 191help: 192 mill -i xiangshan.runMain $(FPGATOP) --help 193 194version: 195 mill -i xiangshan.runMain $(FPGATOP) --version 196 197jar: 198 mill -i xiangshan.assembly 199 200test-jar: 201 mill -i xiangshan.test.assembly 202 203comp: 204 mill -i xiangshan.compile 205 mill -i xiangshan.test.compile 206 207$(TOP_V): $(SCALA_FILE) 208 mkdir -p $(@D) 209 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 210 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 211 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 212ifeq ($(CHISEL_TARGET),systemverilog) 213 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 214 @git log -n 1 >> .__head__ 215 @git diff >> .__diff__ 216 @sed -i 's/^/\/\// ' .__head__ 217 @sed -i 's/^/\/\//' .__diff__ 218 @cat .__head__ .__diff__ $@ > .__out__ 219 @mv .__out__ $@ 220 @rm .__head__ .__diff__ 221endif 222 223verilog: $(TOP_V) 224 225$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 226 mkdir -p $(@D) 227 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 228 @date -R | tee -a $(TIMELOG) 229 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 230 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 231 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 232ifeq ($(CHISEL_TARGET),systemverilog) 233 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 234 @git log -n 1 >> .__head__ 235 @git diff >> .__diff__ 236 @sed -i 's/^/\/\// ' .__head__ 237 @sed -i 's/^/\/\//' .__diff__ 238 @cat .__head__ .__diff__ $@ > .__out__ 239 @mv .__out__ $@ 240 @rm .__head__ .__diff__ 241ifeq ($(PLDM),1) 242 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 243 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 244else 245ifeq ($(ENABLE_XPROP),1) 246 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 247else 248 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 249endif 250endif 251 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 252endif 253 254sim-verilog: $(SIM_TOP_V) 255 256clean: 257 $(MAKE) -C ./difftest clean 258 rm -rf $(BUILD_DIR) 259 260init: 261 git submodule update --init 262 cd rocket-chip && git submodule update --init cde hardfloat 263 cd openLLC && git submodule update --init openNCB 264 265bump: 266 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 267 268bsp: 269 mill -i mill.bsp.BSP/install 270 271idea: 272 mill -i mill.idea.GenIdea/idea 273 274check-format: 275 mill xiangshan.checkFormat 276 277reformat: 278 mill xiangshan.reformat 279 280# verilator simulation 281emu: sim-verilog 282 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 283 284emu-run: emu 285 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 286 287# vcs simulation 288simv: sim-verilog 289 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 290 291simv-run: 292 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 293 294# palladium simulation 295pldm-build: sim-verilog 296 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 297 298pldm-run: 299 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 300 301pldm-debug: 302 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 303 304include Makefile.test 305 306include src/main/scala/device/standalone/standalone_device.mk 307 308.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 309