fix(PTW): fix exception gen when both af and (pf | gpf) occur (#4540)

When `pte_valid` is true and a page fault or guest page fault occurs,
the original design only treated `ppn_af` as invalid (with

fix(PTW): fix exception gen when both af and (pf | gpf) occur (#4540)

When `pte_valid` is true and a page fault or guest page fault occurs,
the original design only treated `ppn_af` as invalid (without checking
whether the higher bits of ppn are zero). However, in this case, the PMP
check would still be performed, potentially raising the `accessFault`
signal.

This commit fixes the bug by ensuring that if a PMP check fails, only
`accessFault` is raised, and pf or gpf will not be incorrectly asserted.
Therefore, when either pf or gpf is valid, any `accessFault` resulting
from PMP should be ignored.

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fix(PTWCache): hfence_gvma should ignore g bit (#4539)

In "RISC-V Instruction Set Manual: Volume II: Privileged Architecture":
The G bit in all G-stage PTEs is reserved for future standard use. Unti

fix(PTWCache): hfence_gvma should ignore g bit (#4539)

In "RISC-V Instruction Set Manual: Volume II: Privileged Architecture":
The G bit in all G-stage PTEs is reserved for future standard use. Until
its use is defined by a standard extension, it should be cleared by
software for forward compatibility, and must be ignored by hardware.

Co-authored-by: SpecialWeeks <[email protected]>

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fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

Co-authored-by: Yanqin Li <[email protected]>

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fix(LLPTW): each LLPTW entry should use its own s2xlate (#4510)

In the previous design, the input s2xlate signal was directly used to
determine whether to virtualize, but the input signal changed to

fix(LLPTW): each LLPTW entry should use its own s2xlate (#4510)

In the previous design, the input s2xlate signal was directly used to
determine whether to virtualize, but the input signal changed to the
default value 0 due to timing problems, resulting in the use of the
wrong PBMTE.

In fact, LLPTW can handle both virtualized and non-virtualized requests
simultaneously. This information is stored in
entries(i).req_info.s2xlate. By using this signal, we can distinguish
between PBMTEs under different virtualization modes. This commit fixes
the bug.

Co-authored-by: SpecialWeeks <[email protected]>

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fix(prefetch): fix control signals of l1 prefetchers (#4534)

Revert "fix(TLB): should always send onlyS1 req when req_need_gpa (#4… (#4551)

…513)"

This reverts commit 6d07e62cded1f9718c229f7c38d297fed2c95cb8.

At the same time, this commit also fixes a bug w

Revert "fix(TLB): should always send onlyS1 req when req_need_gpa (#4… (#4551)

…513)"

This reverts commit 6d07e62cded1f9718c229f7c38d297fed2c95cb8.

At the same time, this commit also fixes a bug where a onlyS1 request
was issued when `req_need_gpa` was active. In fact, even when
`req_need_gpa` is active, it is necessary to determine whether to issue
allStage, onlyS1, or onlyS2 based on the values of the vsatp or hgatp
registers. The previous approach in
https://github.com/OpenXiangShan/XiangShan/pull/4513 was incorrect, and
the details are as follows:

The process of two-stage address translation:

vaddr -> VS-L2 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> VS-L1 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> VS-L0 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> gpaddr -> G-L1 -> G-L0 -> paddr (last G-Stage)

When a page fault occurs at "G-Stage for VS-Stage" in the diagram, the
corresponding VS-Stage result before the arrow is the gpaddr value to be
written to the *tval register.

However, for example, the required gpaddr comes from VS-L0. Although the
first G-Stage query result for VS-L0 is not needed, it is clear that two
G-Stage requests are required before this, after VS-L2 and VS-L1, in
order to obtain the correct VS-L0 memory access address. If the L1 TLB
directly issues an onlyS1 request, then any G-Stage requests will be
ignored, which is unreasonable.

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submodule(chiselAIA): bump chiselAIA to fix `imsic.toCSR.illegal` (#4546)

fix(StoreQueue): keep readPtr until slave ack when outstanding (#4531)

fix(decode): block the vector decode until vsetvl has committed (#4535)

feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Uti

feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.

After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.

This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.

Thanks, Sam

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timing(StoreMisalignBuffer): fix misalign buffer enq timing (#4493)

* a misalign store will enqueue misalign buffer at s1, and revoke if it
needs at s2

fix(MMU): fix gvpn generate when PTWCache Stage1Hit a napot entry (#4527)

For allStage case, when there is a PageTableCache Stage1Hit, the GVPN is
reconstructed within the PTW. However, this reconst

fix(MMU): fix gvpn generate when PTWCache Stage1Hit a napot entry (#4527)

For allStage case, when there is a PageTableCache Stage1Hit, the GVPN is
reconstructed within the PTW. However, this reconstruction process did
not account for the napot case. This commit fixes the bug.

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fix(LLPTW): should not check g-stage pf when vs-stage pf occured (#4525)

When vs-stage pagefault occurs, check high bits of gvpn for g-stage is
meaningless, and should not report guest page fault.

fix(PTW): should not do pmp check before G-stage finish (#4524)

In https://github.com/OpenXiangShan/XiangShan/pull/4422, For the
virtualized allStage scenario, we attempt to suppress PMP checks unti

fix(PTW): should not do pmp check before G-stage finish (#4524)

In https://github.com/OpenXiangShan/XiangShan/pull/4422, For the
virtualized allStage scenario, we attempt to suppress PMP checks until
the G-stage translation result is returned. However, the approach used
in https://github.com/OpenXiangShan/XiangShan/pull/4422 is to try
ignoring the `accessFault` result when `io.hptw.req.valid` is asserted.

In reality, the `accessFault` signal remains valid because it is
implemented as a `RegEnable`. Therefore, we need to prevent
`sent_to_pmp` from being asserted when sending the G-stage translation
request to HPTW. To address this, we introduce the `vs_finish` signal.
When `vs_finish` is `true.B`, `sent_to_pmp` will be false, thus avoiding
false `accessFault` reports.

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fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 T

fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 TLB. When
`req_need_gpa` is valid, it is sufficient to send an onlyStage1 request
to obtain the guest physical address.

In the original design, multiple cases in the `MuxCase` could be valid
at the same time. For example, when both `csr.vsatp.mode =/= 0.U` and
`csr.hgatp.mode =/= 0.U` are valid, an allStage request would be sent
directly, without considering the `req_need_gpa` condition. This commit
fixes that bug.

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fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstransla

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstranslation caches by executing an
> SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA,
> HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and
> optionally ASIDs or VMIDs) in question, and then executing an
> SFENCE.INVAL.IR instruction.

Some additional information was obtained through
https://github.com/riscv/riscv-isa-manual/issues/1936

However, other instructions may still appear between SFENCE.W.INVAL and
SFENCE.INVAL.IR.
> Translation of any memory accesses during that sequence are subject to
> the usual uncertainty as to which translation (among old and new ones)
> is used.

Moreover, these memory accesses are not entirely unpredictable either.
> Each subsequent memory access will unpredictably use either the old
> translation or the new translation. Other behaviors can't occur.

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fix(difftest): fix sync aia event valid (#4517)

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the c

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the clock

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submodule(ready-to-run): bump nemu ref in ready-to-run (#4523)

fix(CSR): use GEILEN from IMSICParams (#4520)

fix(XSTileWrap): remove useless IMSICAsync (#4515)

Already included in CSR.

fix(Uncache): uncache mm store needs difftest to update goldenmem (#4470)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(AIA): integrate ChiselAIA again (#4509)

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secur

submodule(CoupledL2): parameterize NS assignment (#4507)

This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secure), allowing XiangShan core to function as a secure boot processor
in NoC. For systems that already utilize an MCU for secure boot, access
of XiangShan core should theoretically be non-secure. In the latter
cases, `ENABLE_NS=1` option should be added to the `make` compilation
command.

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