feat(dfx): integerate dfx components (#4312)

fix(StoreQueue): cbo.zero is written to sbuffer only if allocated (#4316)

For misalign store that crosses 16-byte boundary, a store would write
sbuffer twice in one cycle but only takes up one SQ en

fix(StoreQueue): cbo.zero is written to sbuffer only if allocated (#4316)

For misalign store that crosses 16-byte boundary, a store would write
sbuffer twice in one cycle but only takes up one SQ entry. If there is
only one misalign store in SQ, `isCboZeroToSbVec`, which is used to
check if there is any cbo.zero written to sbuffer based on `fuOpType` in
`uop`, may apply wrong `fuOpType` in an empty SQ entry, or lead to
X-state propogation in VCS simulaition.

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fix(dbltrp): set sdt to 0 when exe sret to VU (#4313)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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timing(MainPipe): remove `set_conflict` for tag/meta read (#4295)

* reduce meta/tag read enable generate logic
* when `set_conflict == 1`, request can not go to `s1`, and `write` has
higher priori

timing(MainPipe): remove `set_conflict` for tag/meta read (#4295)

* reduce meta/tag read enable generate logic
* when `set_conflict == 1`, request can not go to `s1`, and `write` has
higher priority to `read`

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fix(Uncache): correct the indexes (#4304)

1. Wrong forward index
2. Duplicate judgment `waitSame` index

fix(LoadQueueUncache): exhaust the various cases of flush (#4300)

**Bug trigger point:**

The flush occurs during the `s_wait` phase. The entry has already passed
the flush trigger condition of `io.

fix(LoadQueueUncache): exhaust the various cases of flush (#4300)

**Bug trigger point:**

The flush occurs during the `s_wait` phase. The entry has already passed
the flush trigger condition of `io.uncache.resp.fire`, leading to no
flush. As a result, `needFlushReg` remains in the register until the
next new entry's `io.uncache.resp.fire`, at which point the normal entry
is flushed, causing the program to stuck.

**Bug analysis:** The granularity of flush handling is too coarse.

In the original calculation:
```
val flush = (needFlush && uncacheState === s_idle) || (io.uncache.resp.fire && needFlushReg)
```
Flush is only handled in two states: `s_idle` and non-`s_idle`. This
distinction makes the handling of the other three non-`s_idle` states
very coarse. In fact, for the remaining three states, there needs to be
corresponding feedback based on when `needFlush` is generated and when
`NeedFlushReg` is delayed in the register.
1. In the `s_req` state, before the uncache request is sent, the flush
can be performed in time, using `needFlush` to prevent the request from
being sent.
2. If the request has been sent and the state reaches `s_resp`, to avoid
mismatch between the uncache request and response, the flush can be only
performed after receiving the uncache response, i.e., use `needFlush ||
needFlushReg` to flush when `io.uncache.resp.fire`.
3. If a flush occurs during the `s_wait` state, it can also prevent a
write-back and use `needFlush` to flush in time.

**Bug Fix:**

For better code readability, the `uncacheState` state machine update is
used here to update the `wire` `flush`. Where `flush` refers to
executing the flush, `needFlush` refers to the signal that triggers the
flush, and `needFlushReg` refers to the flush signal stored for delayed
processing flush.

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submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some

submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some missing XSDebug.

This change move these missing XSDebug outside WhenContext, and add
WireInit to LogUtils' apply, to enable probing some subaccessed data,
like a vec elem with dynamic index.

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fix(StoreQueue): fix threshold condition for fore write sbuffer (#4306)

Previously, `ForceWrite` was conditioned to write dead (60, 55), which
no longer applies after we adjusted `StoreQueueSize`.

fix(StoreQueue): fix threshold condition for fore write sbuffer (#4306)

Previously, `ForceWrite` was conditioned to write dead (60, 55), which
no longer applies after we adjusted `StoreQueueSize`.

---

Now a more reasonable parameterized setting is used.
However, the conditions for optimal performance still need to be tested.

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style(csr): fix typo in CSR (#4310)

fix(xtval): fix xtval when raise intr (#4307)

style(LoadPipe): use `miss_req.bits.cancel` instead of `mq_enq_cancel` (#4296)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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chore(dispatch): remove useless code and files (#4288)

timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic (#4254)

There is no exception misaligned store instruction enters the
misalignbuffer. Due to the exception timing difference genera

timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic (#4254)

There is no exception misaligned store instruction enters the
misalignbuffer. Due to the exception timing difference generated by the
`PMA`, the timing of the misalignbuffer rejection condition is bad
timing, which in turn leads to the bad timing of `feedback_slow.hit`.

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style(Bundles): rewrite bundles with new style (#4274)

fix(MainPipe): fix `s1_way_en` generate logic when ecc inject occur (#4285)

* When inject tag ecc error `io.pseudo_error.valid == 1` and mainpipe
request valid (for example `io.miss_req.valid == 1`

fix(MainPipe): fix `s1_way_en` generate logic when ecc inject occur (#4285)

* When inject tag ecc error `io.pseudo_error.valid == 1` and mainpipe
request valid (for example `io.miss_req.valid == 1`
```
val s1_need_replacement = s1_req.miss && !s1_tag_match
val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing
val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way)
```
when generate `s1_way_en`, `s1_tag_match == 0` cause inject tag ecc
error, so `s1_need_replacement == 1`, but may be target cacheline
already in dcache (for example `prefetch.w` miss), finally there is 2
same paddr cacheline in dcache, obviously this is illegal.

* Determine whether it is a pseudo error. If it's pseudo error, use
no-toggled-tag (which no toggled by cacheCtrl) for generate `s1_way_en`,
otherwise use toggled-tag

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fix(LDU): only tlb hit can use tlb resp (#4293)

feat(busytable): support eliminate old vd in new dispatch (#4198)

fix(LoadUnit): corrupt should be triggered on valid mshr (#4292)

fix(Soc, CoupledL2): correct port width of CHI Issue C (#4290)

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags,

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags, fcsr,
* vxsat, vcsr, vstart,
* mstatus, sstatus, hstatus, vsstatus, mnstatus,
* dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
by Use-Level instruction without any fence, and executing OoO would
get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
need to let reading PMC CSRs inorder.

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area(TagArray): split `TagArray` from 4way to 2way per array (#4287)

fix(Uncache): handle flush (#4230)

timing(icache): restore the relaxation of ICG for icache data (#4255)

Revert #4246