1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# L2 cache size in KB 81ifneq ($(L2_CACHE_SIZE),) 82COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 83endif 84 85# L3 cache size in KB 86ifneq ($(L3_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 88endif 89 90# seperate bus for DebugModule 91ifeq ($(SEPERATE_DM_BUS),1) 92COMMON_EXTRA_ARGS += --seperate-dm-bus 93endif 94 95# configuration from yaml file 96ifneq ($(YAML_CONFIG),) 97COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 98endif 99 100# public args sumup 101RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 102DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 103override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 104 105# co-simulation with DRAMsim3 106ifeq ($(WITH_DRAMSIM3),1) 107ifndef DRAMSIM3_HOME 108$(error DRAMSIM3_HOME is not set) 109endif 110override SIM_ARGS += --with-dramsim3 111endif 112 113# run emu with chisel-db 114ifeq ($(WITH_CHISELDB),1) 115override SIM_ARGS += --with-chiseldb 116endif 117 118# run emu with chisel-db 119ifeq ($(WITH_ROLLINGDB),1) 120override SIM_ARGS += --with-rollingdb 121endif 122 123# enable ResetGen 124ifeq ($(WITH_RESETGEN),1) 125override SIM_ARGS += --reset-gen 126endif 127 128# run with disable all perf 129ifeq ($(DISABLE_PERF),1) 130override SIM_ARGS += --disable-perf 131endif 132 133# run with disable all db 134ifeq ($(DISABLE_ALWAYSDB),1) 135override SIM_ARGS += --disable-alwaysdb 136endif 137 138# dynamic switch CONSTANTIN 139ifeq ($(WITH_CONSTANTIN),1) 140override SIM_ARGS += --with-constantin 141endif 142 143# emu for the release version 144RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 145DEBUG_ARGS += --enable-difftest 146override PLDM_ARGS += --enable-difftest 147ifeq ($(RELEASE),1) 148override SIM_ARGS += $(RELEASE_ARGS) 149else ifeq ($(PLDM),1) 150override SIM_ARGS += $(PLDM_ARGS) 151else 152override SIM_ARGS += $(DEBUG_ARGS) 153endif 154 155# use RELEASE_ARGS for TopMain by default 156ifeq ($(PLDM), 1) 157TOPMAIN_ARGS += $(PLDM_ARGS) 158else 159TOPMAIN_ARGS += $(RELEASE_ARGS) 160endif 161 162TIMELOG = $(BUILD_DIR)/time.log 163TIME_CMD = time -avp -o $(TIMELOG) 164 165ifeq ($(PLDM),1) 166SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 167SED_ENDIF = `endif // not def SYNTHESIS 168endif 169 170.DEFAULT_GOAL = verilog 171 172help: 173 mill -i xiangshan.runMain $(FPGATOP) --help 174 175version: 176 mill -i xiangshan.runMain $(FPGATOP) --version 177 178jar: 179 mill -i xiangshan.assembly 180 181test-jar: 182 mill -i xiangshan.test.assembly 183 184$(TOP_V): $(SCALA_FILE) 185 mkdir -p $(@D) 186 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 187 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 188 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 189ifeq ($(CHISEL_TARGET),systemverilog) 190 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 191 @git log -n 1 >> .__head__ 192 @git diff >> .__diff__ 193 @sed -i 's/^/\/\// ' .__head__ 194 @sed -i 's/^/\/\//' .__diff__ 195 @cat .__head__ .__diff__ $@ > .__out__ 196 @mv .__out__ $@ 197 @rm .__head__ .__diff__ 198endif 199 200verilog: $(TOP_V) 201 202$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 203 mkdir -p $(@D) 204 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 205 @date -R | tee -a $(TIMELOG) 206 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 207 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 208 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 209ifeq ($(CHISEL_TARGET),systemverilog) 210 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 211 @git log -n 1 >> .__head__ 212 @git diff >> .__diff__ 213 @sed -i 's/^/\/\// ' .__head__ 214 @sed -i 's/^/\/\//' .__diff__ 215 @cat .__head__ .__diff__ $@ > .__out__ 216 @mv .__out__ $@ 217 @rm .__head__ .__diff__ 218ifeq ($(PLDM),1) 219 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 220 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 221else 222ifeq ($(ENABLE_XPROP),1) 223 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 224else 225 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 226endif 227endif 228 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 229endif 230 231sim-verilog: $(SIM_TOP_V) 232 233clean: 234 $(MAKE) -C ./difftest clean 235 rm -rf $(BUILD_DIR) 236 237init: 238 git submodule update --init 239 cd rocket-chip && git submodule update --init cde hardfloat 240 cd openLLC && git submodule update --init openNCB 241 242bump: 243 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 244 245bsp: 246 mill -i mill.bsp.BSP/install 247 248idea: 249 mill -i mill.idea.GenIdea/idea 250 251check-format: 252 mill xiangshan.checkFormat 253 254reformat: 255 mill xiangshan.reformat 256 257# verilator simulation 258emu: sim-verilog 259 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 260 261emu-run: emu 262 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 263 264# vcs simulation 265simv: sim-verilog 266 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 267 268simv-run: 269 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 270 271# palladium simulation 272pldm-build: sim-verilog 273 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 274 275pldm-run: 276 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 277 278pldm-debug: 279 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 280 281include Makefile.test 282 283include src/main/scala/device/standalone/standalone_device.mk 284 285.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 286