xref: /XiangShan/scripts/top-down/configs.py (revision 914bbc865acb565ce0fae9e50a787f2ab3c57b3a) 
1stats_dir = ''
2
3CSV_PATH = 'results/results.csv'
4JSON_FILE = 'resources/spec06_rv64gcb_o2_20m.json'
5OUT_CSV = 'results/results-weighted.csv'
6INT_ONLY = False
7FP_ONLY = False
8
9xs_coarse_rename_map = {
10    'OverrideBubble': 'MergeFrontend',
11    'FtqFullStall': 'MergeFrontend',
12    'FtqUpdateBubble': 'MergeBadSpec',
13    'TAGEMissBubble': 'MergeBadSpec',
14    'SCMissBubble': 'MergeBadSpec',
15    'ITTAGEMissBubble': 'MergeBadSpec',
16    'RASMissBubble': 'MergeBadSpec',
17    'ICacheMissBubble': 'MergeFrontend',
18    'ITLBMissBubble': 'MergeFrontend',
19    'BTBMissBubble': 'MergeBadSpec',
20    'FetchFragBubble': 'MergeFrontend',
21
22    'DivStall': 'MergeCore',
23    'IntNotReadyStall': 'MergeCore',
24    'FPNotReadyStall': 'MergeCore',
25
26    'MemNotReadyStall': 'MergeLoad',
27
28    'IntFlStall': 'MergeFreelistStall',
29    'FpFlStall': 'MergeFreelistStall',
30
31    'LoadTLBStall': 'MergeLoad',
32    'LoadL1Stall': 'MergeLoad',
33    'LoadL2Stall': 'MergeLoad',
34    'LoadL3Stall': 'MergeLoad',
35    'LoadMemStall': 'MergeLoad',
36    'StoreStall': 'MergeStore',
37
38    'AtomicStall': 'MergeMisc',
39
40    'FlushedInsts': 'MergeBadSpecInst',
41    'LoadVioReplayStall': 'MergeBadSpec',
42
43    'LoadMSHRReplayStall': 'MergeLoad',
44
45    'ControlRecoveryStall': 'MergeBadSpec',
46    'MemVioRecoveryStall': 'MergeBadSpec',
47    'OtherRecoveryStall': 'MergeBadSpec',
48
49    'OtherCoreStall': 'MergeCoreOther',
50    'NoStall': 'MergeBase',
51
52    'MemVioRedirectBubble': 'MergeBadSpec',
53    'OtherRedirectBubble': 'MergeMisc',
54
55    'commitInstr': 'Insts',
56    'total_cycles': 'Cycles',
57}
58
59xs_fine_grain_rename_map = {
60    'OverrideBubble': 'MergeOtherFrontend',
61    'FtqFullStall': 'MergeOtherFrontend',
62    'FtqUpdateBubble': 'MergeBadSpecBubble',
63    'TAGEMissBubble': 'MergeBadSpecBubble',
64    'SCMissBubble': 'MergeBadSpecBubble',
65    'ITTAGEMissBubble': 'MergeBadSpecBubble',
66    'RASMissBubble': 'MergeBadSpecBubble',
67    'ICacheMissBubble': 'ICacheBubble',
68    'ITLBMissBubble': 'ITlbBubble',
69    'BTBMissBubble': 'MergeBadSpecBubble',
70    'FetchFragBubble': 'FragmentBubble',
71
72    'DivStall': 'LongExecute',
73    'IntNotReadyStall': 'MergeInstNotReady',
74    'FPNotReadyStall': 'MergeInstNotReady',
75
76    'MemNotReadyStall': 'MemNotReady',
77
78    'IntFlStall': 'MergeFreelistStall',
79    'FpFlStall': 'MergeFreelistStall',
80
81    'LoadTLBStall': 'DTlbStall',
82    'LoadL1Stall': 'LoadL1Bound',
83    'LoadL2Stall': 'LoadL2Bound',
84    'LoadL3Stall': 'LoadL3Bound',
85    'LoadMemStall': 'LoadMemBound',
86    'StoreStall': 'MergeStoreBound',
87
88    'AtomicStall': 'SerializeStall',
89
90    'FlushedInsts': 'BadSpecInst',
91    'LoadVioReplayStall': None,
92
93    'LoadMSHRReplayStall': None,
94
95    'ControlRecoveryStall': 'MergeBadSpecWalking',
96    'MemVioRecoveryStall': 'MergeBadSpecWalking',
97    'OtherRecoveryStall': 'MergeBadSpecWalking',
98
99    'OtherCoreStall': 'MergeMisc',
100    'NoStall': None,
101
102    'MemVioRedirectBubble': 'MergeBadSpecBubble',
103    'OtherRedirectBubble': 'MergeMisc',
104
105    'commitInstr': 'Insts',
106    'total_cycles': 'Cycles',
107}
108
109XS_CORE_PREFIX = r'\[PERF \]\[time=\s+\d+\] TOP\.SimTop\.l_soc\.core_with_l2\.core'
110
111targets = {
112    'NoStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: NoStall,\s+(\d+)',
113
114    'OverrideBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: OverrideBubble,\s+(\d+)',
115    'FtqUpdateBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FtqUpdateBubble,\s+(\d+)',
116    'TAGEMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: TAGEMissBubble,\s+(\d+)',
117    'SCMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: SCMissBubble,\s+(\d+)',
118    'ITTAGEMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: ITTAGEMissBubble,\s+(\d+)',
119    'RASMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: RASMissBubble,\s+(\d+)',
120    'MemVioRedirectBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: MemVioRedirectBubble,\s+(\d+)',
121    'OtherRedirectBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: OtherRedirectBubble,\s+(\d+)',
122    'FtqFullStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FtqFullStall,\s+(\d+)',
123
124    'ICacheMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: ICacheMissBubble,\s+(\d+)',
125    'ITLBMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: ITLBMissBubble,\s+(\d+)',
126    'BTBMissBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: BTBMissBubble,\s+(\d+)',
127    'FetchFragBubble': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FetchFragBubble,\s+(\d+)',
128
129    'DivStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: DivStall,\s+(\d+)',
130    'IntNotReadyStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: IntNotReadyStall,\s+(\d+)',
131    'FPNotReadyStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FPNotReadyStall,\s+(\d+)',
132    'MemNotReadyStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: MemNotReadyStall,\s+(\d+)',
133
134    'IntFlStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: IntFlStall,\s+(\d+)',
135    'FpFlStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FpFlStall,\s+(\d+)',
136
137    'LoadTLBStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadTLBStall,\s+(\d+)',
138    'LoadL1Stall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadL1Stall,\s+(\d+)',
139    'LoadL2Stall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadL2Stall,\s+(\d+)',
140    'LoadL3Stall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadL3Stall,\s+(\d+)',
141    'LoadMemStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadMemStall,\s+(\d+)',
142    'StoreStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: StoreStall,\s+(\d+)',
143    'AtomicStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: AtomicStall,\s+(\d+)',
144
145    'LoadVioReplayStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadVioReplayStall,\s+(\d+)',
146    'LoadMSHRReplayStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadMSHRReplayStall,\s+(\d+)',
147
148    'ControlRecoveryStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: ControlRecoveryStall,\s+(\d+)',
149    'MemVioRecoveryStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: MemVioRecoveryStall,\s+(\d+)',
150    'OtherRecoveryStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: OtherRecoveryStall,\s+(\d+)',
151
152    'FlushedInsts': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FlushedInsts,\s+(\d+)',
153    'OtherCoreStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: OtherCoreStall,\s+(\d+)',
154
155    "commitInstr": r"\[PERF \]\[time=\s+\d+\] TOP.SimTop.l_soc.core_with_l2.core.backend.ctrlBlock.rob: commitInstr,\s+(\d+)",
156    "total_cycles": r"\[PERF \]\[time=\s+\d+\] TOP.SimTop.l_soc.core_with_l2.core.backend.ctrlBlock.rob: clock_cycle,\s+(\d+)",
157}
158
159
160spec_bmks = {
161    '06': {
162        'int': [
163            'perlbench',
164            'bzip2',
165            'gcc',
166            'mcf',
167            'gobmk',
168            'hmmer',
169            'sjeng',
170            'libquantum',
171            'h264ref',
172            'omnetpp',
173            'astar',
174            'xalancbmk',
175        ],
176        'float': [
177            'bwaves', 'gamess', 'milc', 'zeusmp', 'gromacs',
178            'cactusADM', 'leslie3d', 'namd', 'dealII', 'soplex',
179            'povray', 'calculix', 'GemsFDTD', 'tonto', 'lbm',
180            'wrf', 'sphinx3',
181        ],
182        'high_squash': ['astar', 'bzip2', 'gobmk', 'sjeng'],
183    },
184    '17': {},
185}
186