1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# IMSIC use TileLink rather than AXI4Lite 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --enable-dfx 83endif 84 85# L2 cache size in KB 86ifneq ($(L2_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 88endif 89 90# L3 cache size in KB 91ifneq ($(L3_CACHE_SIZE),) 92COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 93endif 94 95# seperate bus for DebugModule 96ifeq ($(SEPERATE_DM_BUS),1) 97COMMON_EXTRA_ARGS += --seperate-dm-bus 98endif 99 100# configuration from yaml file 101ifneq ($(YAML_CONFIG),) 102COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 103endif 104 105# public args sumup 106RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 107DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 108override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 109 110# co-simulation with DRAMsim3 111ifeq ($(WITH_DRAMSIM3),1) 112ifndef DRAMSIM3_HOME 113$(error DRAMSIM3_HOME is not set) 114endif 115override SIM_ARGS += --with-dramsim3 116endif 117 118# run emu with chisel-db 119ifeq ($(WITH_CHISELDB),1) 120override SIM_ARGS += --with-chiseldb 121endif 122 123# run emu with chisel-db 124ifeq ($(WITH_ROLLINGDB),1) 125override SIM_ARGS += --with-rollingdb 126endif 127 128# enable ResetGen 129ifeq ($(WITH_RESETGEN),1) 130override SIM_ARGS += --reset-gen 131endif 132 133# run with disable all perf 134ifeq ($(DISABLE_PERF),1) 135override SIM_ARGS += --disable-perf 136endif 137 138# run with disable all db 139ifeq ($(DISABLE_ALWAYSDB),1) 140override SIM_ARGS += --disable-alwaysdb 141endif 142 143# dynamic switch CONSTANTIN 144ifeq ($(WITH_CONSTANTIN),1) 145override SIM_ARGS += --with-constantin 146endif 147 148# emu for the release version 149RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 150DEBUG_ARGS += --enable-difftest 151override PLDM_ARGS += --enable-difftest 152ifeq ($(RELEASE),1) 153override SIM_ARGS += $(RELEASE_ARGS) 154else ifeq ($(PLDM),1) 155override SIM_ARGS += $(PLDM_ARGS) 156else 157override SIM_ARGS += $(DEBUG_ARGS) 158endif 159 160# use RELEASE_ARGS for TopMain by default 161ifeq ($(PLDM), 1) 162TOPMAIN_ARGS += $(PLDM_ARGS) 163else 164TOPMAIN_ARGS += $(RELEASE_ARGS) 165endif 166 167TIMELOG = $(BUILD_DIR)/time.log 168TIME_CMD = time -avp -o $(TIMELOG) 169 170ifeq ($(PLDM),1) 171SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 172SED_ENDIF = `endif // not def SYNTHESIS 173endif 174 175.DEFAULT_GOAL = verilog 176 177help: 178 mill -i xiangshan.runMain $(FPGATOP) --help 179 180version: 181 mill -i xiangshan.runMain $(FPGATOP) --version 182 183jar: 184 mill -i xiangshan.assembly 185 186test-jar: 187 mill -i xiangshan.test.assembly 188 189comp: 190 mill -i xiangshan.compile 191 mill -i xiangshan.test.compile 192 193$(TOP_V): $(SCALA_FILE) 194 mkdir -p $(@D) 195 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 196 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 197 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 198ifeq ($(CHISEL_TARGET),systemverilog) 199 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 200 @git log -n 1 >> .__head__ 201 @git diff >> .__diff__ 202 @sed -i 's/^/\/\// ' .__head__ 203 @sed -i 's/^/\/\//' .__diff__ 204 @cat .__head__ .__diff__ $@ > .__out__ 205 @mv .__out__ $@ 206 @rm .__head__ .__diff__ 207endif 208 209verilog: $(TOP_V) 210 211$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 212 mkdir -p $(@D) 213 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 214 @date -R | tee -a $(TIMELOG) 215 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 216 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 217 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 218ifeq ($(CHISEL_TARGET),systemverilog) 219 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 220 @git log -n 1 >> .__head__ 221 @git diff >> .__diff__ 222 @sed -i 's/^/\/\// ' .__head__ 223 @sed -i 's/^/\/\//' .__diff__ 224 @cat .__head__ .__diff__ $@ > .__out__ 225 @mv .__out__ $@ 226 @rm .__head__ .__diff__ 227ifeq ($(PLDM),1) 228 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 229 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 230else 231ifeq ($(ENABLE_XPROP),1) 232 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 233else 234 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 235endif 236endif 237 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 238endif 239 240sim-verilog: $(SIM_TOP_V) 241 242clean: 243 $(MAKE) -C ./difftest clean 244 rm -rf $(BUILD_DIR) 245 246init: 247 git submodule update --init 248 cd rocket-chip && git submodule update --init cde hardfloat 249 cd openLLC && git submodule update --init openNCB 250 251bump: 252 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 253 254bsp: 255 mill -i mill.bsp.BSP/install 256 257idea: 258 mill -i mill.idea.GenIdea/idea 259 260check-format: 261 mill xiangshan.checkFormat 262 263reformat: 264 mill xiangshan.reformat 265 266# verilator simulation 267emu: sim-verilog 268 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 269 270emu-run: emu 271 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 272 273# vcs simulation 274simv: sim-verilog 275 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 276 277simv-run: 278 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 279 280# palladium simulation 281pldm-build: sim-verilog 282 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 283 284pldm-run: 285 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 286 287pldm-debug: 288 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 289 290include Makefile.test 291 292include src/main/scala/device/standalone/standalone_device.mk 293 294.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 295