debug - OpenGrok history log for /XiangShan/debug

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
598e480f	31-Oct-2020	jinyue110 <[email protected]>	L1plusCache: fix bug that flush didn't change valid_array Makefile /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala
b7959e5f	30-Oct-2020	jinyue110 <[email protected]>	PASS coremark and microbench but loader(fence.i) FAIL Makefile /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala
6f763b2d	30-Oct-2020	jinyue110 <[email protected]>	connect l1pluscache into memory hierarchy Makefile /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala
3d841bdf	29-Oct-2020	jinyue110 <[email protected]>	Merge branch 'master' into icache-missqueue /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala
5873524f	28-Oct-2020	LinJiawei <[email protected]>	Merge remote-tracking branch 'origin/fix-modulename-in-chiseltest' into update-chisel /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala
903af6a2	24-Oct-2020	LinJiawei <[email protected]>	PrintModuleName: must run after wiring transform /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive Makefile /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala
84959497	21-Oct-2020	jinyue110 <[email protected]>	icacheMissQueue: support different client visit Makefile /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala
e1f91fc1	21-Oct-2020	William Wang <[email protected]>	[WIP] Lsq: fix stq forward & rollback logic /XiangShan/Makefile Makefile /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/top/XSSim.scala
3c20517c	20-Oct-2020	jinyue110 <[email protected]>	icacheMissQueue: done and PASS coremark and microbench Makefile /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala
118c6c3c	20-Oct-2020	jinyue110 <[email protected]>	icacheMissQueue: fix bug that s_write_back deadlock Makefile /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala
a684b6ff	19-Oct-2020	jinyue110 <[email protected]>	icacheMissQueue: add debug info and fix deadlock bug Makefile /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala
09bd5547	19-Oct-2020	jinyue110 <[email protected]>	icacheMissQueue: fix syntax bug /XiangShan/Makefile Makefile /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/XSSim.scala
91e72918	15-Oct-2020	LinJiawei <[email protected]>	debug/Makefile: keep it clean Makefile
9a1283b6	14-Oct-2020	jinyue110 <[email protected]>	BPU: ret instruction taken depend on btb hit when spec ras is empty /XiangShan/Makefile Makefile /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/noop/fu/FPU.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/isa/RVD.scala /XiangShan/src/main/scala/noop/isa/RVF.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Classify.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/README.md /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/RoundingUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/LZA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/package.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ORTree.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/top/XSSim.scala
b2bf5b8d	07-Oct-2020	LinJiawei <[email protected]>	[WIP] perf_sbuffer.sh: a srcipt to help debugging sbuffer perf /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile perf_sbuffer.sh /XiangShan/ready-to-run/bbl.bin /XiangShan/ready-to-run/linux.bin /XiangShan/ready-to-run/microbench.bin /XiangShan/ready-to-run/riscv64-nemu-interpreter-so /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/top/XSSim.scala
0a019f1c	08-Sep-2020	jinyue110 <[email protected]>	icache: add mmio address surpport Makefile /XiangShan/src/main/scala/xiangshan/cache/icache.scala
b21206a8	07-Sep-2020	jinyue110 <[email protected]>	Merge branch 'dev-icache' of https://github.com/RISCVERS/XiangShan into dev-icache /XiangShan/.gitmodules /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
7ccd034b	07-Sep-2020	jinyue110 <[email protected]>	icache: add performance counter Makefile /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala
dbe84653	07-Sep-2020	Allen <[email protected]>	Merge branch 'l2cache' into dev-icache /XiangShan/.gitmodules /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
5c979681	07-Sep-2020	jinyue110 <[email protected]>	icache: fix some print error Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala
35727b1c	04-Sep-2020	jinyue110 <[email protected]>	icache: add cutHelper Makefile /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala
d7fd0e77	03-Sep-2020	LinJiawei <[email protected]>	Update unit test /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/.mill-jvm-opts /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/AXI4ToAXI4Lite.scala /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTL1toN.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/miscMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLBurstMaster.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
23814de3	01-Sep-2020	jinyue110 <[email protected]>	icache: add pipeline trait /XiangShan/.github/workflows/emu.yml Makefile /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala
26c396c4	31-Aug-2020	jinyue110 <[email protected]>	icache: change acquire into get and delete mem Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/scala/top/XSSim.scala
1ff15c59	26-Aug-2020	jinyue110 <[email protected]>	BPU: fix bug BPU and icache is not synchronous BPU doesn't know icahce miss and will not stall pipeline /XiangShan/.gitmodules /XiangShan/.mill-jvm-opts /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLBurstMaster.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
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