1package device 2 3import chisel3._ 4import chisel3.util.experimental.BoringUtils 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.AddressSet 7import utils._ 8 9class TimerIO extends Bundle { 10 val mtip = Output(Bool()) 11} 12 13class AXI4Timer 14( 15 sim: Boolean = false, 16 address: AddressSet 17)(implicit p: Parameters) 18 extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO) 19{ 20 override lazy val module = new AXI4SlaveModuleImp[TimerIO](this){ 21 val mtime = RegInit(0.U(64.W)) // unit: us 22 val mtimecmp = RegInit(0.U(64.W)) 23 24 val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000) 25 val freq = RegInit(clk.U(16.W)) 26 val inc = RegInit(1000.U(16.W)) 27 28 val cnt = RegInit(0.U(16.W)) 29 val nextCnt = cnt + 1.U 30 cnt := Mux(nextCnt < freq, nextCnt, 0.U) 31 val tick = (nextCnt === freq) 32 when (tick) { mtime := mtime + inc } 33 34 if (sim) { 35 val isWFI = WireInit(false.B) 36 BoringUtils.addSink(isWFI, "isWFI") 37 when (isWFI) { mtime := mtime + 100000.U } 38 } 39 40 val mapping = Map( 41 RegMap(0x4000, mtimecmp), 42 RegMap(0x8000, freq), 43 RegMap(0x8008, inc), 44 RegMap(0xbff8, mtime) 45 ) 46 def getOffset(addr: UInt) = addr(15,0) 47 48 RegMap.generate(mapping, getOffset(raddr), in.r.bits.data, 49 getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb)) 50 51 io.extra.get.mtip := RegNext(mtime >= mtimecmp) 52 } 53} 54