1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 6import top.Parameters 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.cache.{ICache,DCache, DCacheParameters, ICacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLClientNode, TLIdentityNode, TLXbar} 16import utils._ 17 18case class XSCoreParameters 19( 20 XLEN: Int = 64, 21 HasMExtension: Boolean = true, 22 HasCExtension: Boolean = true, 23 HasDiv: Boolean = true, 24 HasICache: Boolean = true, 25 HasDCache: Boolean = true, 26 EnableStoreQueue: Boolean = true, 27 AddrBits: Int = 64, 28 VAddrBits: Int = 39, 29 PAddrBits: Int = 40, 30 HasFPU: Boolean = true, 31 FectchWidth: Int = 8, 32 EnableBPU: Boolean = true, 33 EnableBPD: Boolean = true, 34 EnableRAS: Boolean = false, 35 EnableLB: Boolean = false, 36 HistoryLength: Int = 64, 37 BtbSize: Int = 256, 38 JbtacSize: Int = 1024, 39 JbtacBanks: Int = 8, 40 RasSize: Int = 16, 41 CacheLineSize: Int = 512, 42 UBtbWays: Int = 16, 43 BtbWays: Int = 2, 44 IBufSize: Int = 64, 45 DecodeWidth: Int = 6, 46 RenameWidth: Int = 6, 47 CommitWidth: Int = 6, 48 BrqSize: Int = 16, 49 IssQueSize: Int = 8, 50 NRPhyRegs: Int = 128, 51 NRIntReadPorts: Int = 8, 52 NRIntWritePorts: Int = 8, 53 NRFpReadPorts: Int = 14, 54 NRFpWritePorts: Int = 8, 55 LsroqSize: Int = 16, 56 RoqSize: Int = 32, 57 dpParams: DispatchParameters = DispatchParameters( 58 DqEnqWidth = 4, 59 IntDqSize = 64, 60 FpDqSize = 64, 61 LsDqSize = 64, 62 IntDqDeqWidth = 4, 63 FpDqDeqWidth = 4, 64 LsDqDeqWidth = 4, 65 IntDqReplayWidth = 4, 66 FpDqReplayWidth = 4, 67 LsDqReplayWidth = 4 68 ), 69 exuParameters: ExuParameters = ExuParameters( 70 JmpCnt = 1, 71 AluCnt = 4, 72 MulCnt = 0, 73 MduCnt = 2, 74 FmacCnt = 0, 75 FmiscCnt = 0, 76 FmiscDivSqrtCnt = 0, 77 LduCnt = 2, 78 StuCnt = 2 79 ), 80 LoadPipelineWidth: Int = 2, 81 StorePipelineWidth: Int = 2, 82 StoreBufferSize: Int = 16, 83 RefillSize: Int = 512, 84 TlbEntrySize: Int = 32, 85 TlbL2EntrySize: Int = 256, // or 512 86 PtwL1EntrySize: Int = 16, 87 PtwL2EntrySize: Int = 256 88) 89 90trait HasXSParameter { 91 92 val core = Parameters.get.coreParameters 93 val env = Parameters.get.envParameters 94 95 val XLEN = core.XLEN 96 val HasMExtension = core.HasMExtension 97 val HasCExtension = core.HasCExtension 98 val HasDiv = core.HasDiv 99 val HasIcache = core.HasICache 100 val HasDcache = core.HasDCache 101 val EnableStoreQueue = core.EnableStoreQueue 102 val AddrBits = core.AddrBits // AddrBits is used in some cases 103 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 104 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 105 val AddrBytes = AddrBits / 8 // unused 106 val DataBits = XLEN 107 val DataBytes = DataBits / 8 108 val HasFPU = core.HasFPU 109 val FetchWidth = core.FectchWidth 110 val PredictWidth = FetchWidth * 2 111 val EnableBPU = core.EnableBPU 112 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 113 val EnableRAS = core.EnableRAS 114 val EnableLB = core.EnableLB 115 val HistoryLength = core.HistoryLength 116 val BtbSize = core.BtbSize 117 // val BtbWays = 4 118 val BtbBanks = PredictWidth 119 // val BtbSets = BtbSize / BtbWays 120 val JbtacSize = core.JbtacSize 121 val JbtacBanks = core.JbtacBanks 122 val RasSize = core.RasSize 123 val CacheLineSize = core.CacheLineSize 124 val CacheLineHalfWord = CacheLineSize / 16 125 val ExtHistoryLength = HistoryLength * 2 126 val UBtbWays = core.UBtbWays 127 val BtbWays = core.BtbWays 128 val IBufSize = core.IBufSize 129 val DecodeWidth = core.DecodeWidth 130 val RenameWidth = core.RenameWidth 131 val CommitWidth = core.CommitWidth 132 val BrqSize = core.BrqSize 133 val IssQueSize = core.IssQueSize 134 val BrTagWidth = log2Up(BrqSize) 135 val NRPhyRegs = core.NRPhyRegs 136 val PhyRegIdxWidth = log2Up(NRPhyRegs) 137 val LsroqSize = core.LsroqSize // 64 138 val RoqSize = core.RoqSize 139 val InnerRoqIdxWidth = log2Up(RoqSize) 140 val RoqIdxWidth = InnerRoqIdxWidth + 1 141 val InnerLsroqIdxWidth = log2Up(LsroqSize) 142 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 143 val dpParams = core.dpParams 144 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 145 val exuParameters = core.exuParameters 146 val NRIntReadPorts = core.NRIntReadPorts 147 val NRIntWritePorts = core.NRIntWritePorts 148 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 149 val NRFpReadPorts = core.NRFpReadPorts 150 val NRFpWritePorts = core.NRFpWritePorts 151 val LoadPipelineWidth = core.LoadPipelineWidth 152 val StorePipelineWidth = core.StorePipelineWidth 153 val StoreBufferSize = core.StoreBufferSize 154 val RefillSize = core.RefillSize 155 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 156 val TlbEntrySize = core.TlbEntrySize 157 val TlbL2EntrySize = core.TlbL2EntrySize 158 val PtwL1EntrySize = core.PtwL1EntrySize 159 val PtwL2EntrySize = core.PtwL2EntrySize 160 161 val l1BusDataWidth = 64 162 163 val icacheParameters = ICacheParameters( 164 ) 165 166 val LRSCCycles = 16 167 val dcacheParameters = DCacheParameters( 168 tagECC = Some("secded"), 169 dataECC = Some("secded") 170 ) 171} 172 173trait HasXSLog { this: RawModule => 174 implicit val moduleName: String = this.name 175} 176 177abstract class XSModule extends Module 178 with HasXSParameter 179 with HasExceptionNO 180 with HasXSLog 181 182//remove this trait after impl module logic 183trait NeedImpl { this: Module => 184 override protected def IO[T <: Data](iodef: T): T = { 185 val io = chisel3.experimental.IO(iodef) 186 io <> DontCare 187 io 188 } 189} 190 191abstract class XSBundle extends Bundle 192 with HasXSParameter 193 194case class EnviromentParameters 195( 196 FPGAPlatform: Boolean = true, 197 EnableDebug: Boolean = false 198) 199 200object AddressSpace extends HasXSParameter { 201 // (start, size) 202 // address out of MMIO will be considered as DRAM 203 def mmio = List( 204 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 205 (0x40000000L, 0x40000000L) // external devices 206 ) 207 208 def isMMIO(addr: UInt): Bool = mmio.map(range => { 209 require(isPow2(range._2)) 210 val bits = log2Up(range._2) 211 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 212 }).reduce(_ || _) 213} 214 215 216 217class XSCore()(implicit p: config.Parameters) extends LazyModule { 218 219 val dcache = LazyModule(new DCache()) 220 val uncache = LazyModule(new Uncache()) 221 val icache = LazyModule(new ICache()) 222 val ptw = LazyModule(new PTW()) 223 224 // TODO: crossbar Icache/Dcache/PTW here 225 val mem = TLXbar() 226 val mmio = uncache.clientNode 227 228 mem := TLCacheCork(sinkIds = 1) := dcache.clientNode 229 mem := TLCacheCork(sinkIds = 1) := icache.clientNode 230 mem := TLCacheCork(sinkIds = 1) := ptw.node 231 232 lazy val module = new XSCoreImp(this) 233} 234 235class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 236 237 val front = Module(new Frontend) 238 val backend = Module(new Backend) 239 val mem = Module(new Memend) 240 241 val dcache = outer.dcache.module 242 val uncache = outer.uncache.module 243 val icache = outer.icache.module 244 val ptw = outer.ptw.module 245 246 // TODO: connect this 247 dcache.io.lsu.misc <> DontCare 248 249 front.io.backend <> backend.io.frontend 250 front.io.icacheResp <> icache.io.resp 251 icache.io.req <> front.io.icacheReq 252 icache.io.flush <> front.io.icacheFlush 253 mem.io.backend <> backend.io.mem 254 255 ptw.io.tlb(0) <> mem.io.ptw 256 ptw.io.tlb(1) <> DontCare 257 258 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 259 dcache.io.lsu.lsroq <> mem.io.miscToDcache 260 dcache.io.lsu.store <> mem.io.sbufferToDcache 261 uncache.io.lsroq <> mem.io.uncache 262 263} 264