1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8import xiangshan.cache._ 9 10trait HasIFUConst { this: XSModule => 11 val resetVector = 0x80000000L//TODO: set reset vec 12 val groupAlign = log2Up(FetchWidth * 4 * 2) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 // each 1 bit in mask stands for 2 Bytes 15 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 16 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 17} 18 19class IFUIO extends XSBundle 20{ 21 val fetchPacket = DecoupledIO(new FetchPacket) 22 val redirect = Flipped(ValidIO(new Redirect)) 23 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 25 val icacheReq = DecoupledIO(new ICacheReq) 26 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 27 val icacheFlush = Output(UInt(2.W)) 28} 29 30 31class IFU extends XSModule with HasIFUConst 32{ 33 val io = IO(new IFUIO) 34 val bpu = BPU(EnableBPU) 35 val pd = Module(new PreDecode) 36 37 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 38 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 39 40 if4_flush := io.redirect.valid 41 if3_flush := if4_flush || if4_redirect 42 if2_flush := if3_flush || if3_redirect 43 if1_flush := if2_flush || if2_redirect 44 45 //********************** IF1 ****************************// 46 val if1_valid = !reset.asBool && GTimer() > 500.U 47 val if1_npc = WireInit(0.U(VAddrBits.W)) 48 val if2_ready = WireInit(false.B) 49 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 50 51 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 52 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 53 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 54 val shiftPtr = WireInit(false.B) 55 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 56 val ptr = Mux(shiftPtr, newPtr, headPtr) 57 when (shiftPtr) { headPtr := newPtr } 58 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 59 for (i <- 0 until HistoryLength) { 60 hist(i) := extHist(ptr + i.U) 61 } 62 63 newPtr := headPtr 64 shiftPtr := false.B 65 66 //********************** IF2 ****************************// 67 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 68 val if3_ready = WireInit(false.B) 69 val if2_fire = if2_valid && if3_ready && !if2_flush 70 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 71 val if2_snpc = snpc(if2_pc) 72 val if2_histPtr = RegEnable(ptr, if1_fire) 73 if2_ready := if2_fire || !if2_valid || if2_flush 74 when (if2_flush) { if2_valid := if1_fire } 75 .elsewhen (if1_fire) { if2_valid := if1_valid } 76 .elsewhen (if2_fire) { if2_valid := false.B } 77 78 when (RegNext(reset.asBool) && !reset.asBool) { 79 if1_npc := resetVector.U(VAddrBits.W) 80 }.elsewhen (if2_fire) { 81 if1_npc := if2_snpc 82 }.otherwise { 83 if1_npc := RegNext(if1_npc) 84 } 85 86 val if2_bp = bpu.io.out(0).bits 87 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 88 when (if2_redirect) { 89 if1_npc := if2_bp.target 90 } 91 92 when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) { 93 shiftPtr := true.B 94 newPtr := headPtr - 1.U 95 hist(0) := if2_bp.taken.asUInt 96 extHist(newPtr) := if2_bp.taken.asUInt 97 } 98 99 //********************** IF3 ****************************// 100 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 101 val if4_ready = WireInit(false.B) 102 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 103 val if3_pc = RegEnable(if2_pc, if2_fire) 104 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 105 if3_ready := if3_fire || !if3_valid || if3_flush 106 when (if3_flush) { if3_valid := false.B } 107 .elsewhen (if2_fire) { if3_valid := if2_valid } 108 .elsewhen (if3_fire) { if3_valid := false.B } 109 110 val if3_bp = bpu.io.out(1).bits 111 112 class PrevHalfInstr extends Bundle { 113 val valid = Bool() 114 val taken = Bool() 115 val fetchpc = UInt(VAddrBits.W) // only for debug 116 val idx = UInt(VAddrBits.W) // only for debug 117 val pc = UInt(VAddrBits.W) 118 val target = UInt(VAddrBits.W) 119 val instr = UInt(16.W) 120 val ipf = Bool() 121 } 122 123 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 124 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 125 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 126 val crossPageIPF = WireInit(false.B) 127 when (if4_prevHalfInstr.valid) { 128 if3_prevHalfInstr := if4_prevHalfInstr 129 } 130 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 131 132 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 133 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 134 when (if3_redirect) { 135 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 136 } 137 138 when (if3_fire && if3_redirect) { 139 shiftPtr := true.B 140 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 141 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 142 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 143 extHist(if3_histPtr)) 144 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 145 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 146 extHist(if3_histPtr)) 147 } 148 149 150 //********************** IF4 ****************************// 151 val if4_pd = RegEnable(pd.io.out, if3_fire) 152 val if4_ipf = RegEnable(io.icacheResp.bits.ipf || if3_hasPrevHalfInstr && prevHalfInstr.ipf, if3_fire) 153 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 154 val if4_valid = RegInit(false.B) 155 val if4_fire = if4_valid && io.fetchPacket.ready 156 val if4_pc = RegEnable(if3_pc, if3_fire) 157 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 158 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 159 when (if4_flush) { if4_valid := false.B } 160 .elsewhen (if3_fire) { if4_valid := if3_valid } 161 .elsewhen(if4_fire) { if4_valid := false.B } 162 163 val if4_bp = Wire(new BranchPrediction) 164 if4_bp := bpu.io.out(2).bits 165 166 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 167 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 168 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 169 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 170 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 171 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 172 173 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 174 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 175 if4_prevHalfInstr.valid := true.B 176 if4_prevHalfInstr.taken := if4_bp.taken 177 if4_prevHalfInstr.fetchpc := if4_pc 178 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 179 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 180 if4_prevHalfInstr.target := if4_bp.target 181 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 182 if4_prevHalfInstr.ipf := if4_ipf 183 } 184 185 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 186 if4_redirect := true.B 187 shiftPtr := true.B 188 newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 189 hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 190 extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 191 when (if4_bp.saveHalfRVI) { 192 if1_npc := snpc(if4_pc) 193 }.otherwise { 194 if1_npc := if4_bp.target 195 } 196 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 197 when (if4_bp.saveHalfRVI && if4_bp.taken) { 198 if4_redirect := true.B 199 if1_npc := snpc(if4_pc) 200 shiftPtr := true.B 201 newPtr := if4_histPtr - 1.U 202 hist(0) := 1.U 203 extHist(newPtr) := 1.U 204 }.otherwise { 205 if4_redirect := false.B 206 } 207 }.otherwise { 208 if4_redirect := false.B 209 } 210 211 212 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 213 shiftPtr := true.B 214 newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U 215 hist(0) := io.outOfOrderBrInfo.bits.taken 216 extHist(newPtr) := io.outOfOrderBrInfo.bits.taken 217 } 218 219 when (io.redirect.valid) { 220 if1_npc := io.redirect.bits.target 221 } 222 223 io.icacheReq.valid := if1_valid && if2_ready 224 io.icacheReq.bits.addr := if1_npc 225 io.icacheReq.bits.mask := mask(if1_npc) 226 io.icacheResp.ready := if4_ready 227 //io.icacheResp.ready := if3_valid 228 io.icacheFlush := Cat(if3_flush, if2_flush) 229 230 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 231 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 232 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 233 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 234 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 235 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 236 237 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 238 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 239 bpu.io.cacheValid := io.icacheResp.valid 240 bpu.io.in.valid := if1_fire 241 bpu.io.in.bits.pc := if1_npc 242 bpu.io.in.bits.hist := hist.asUInt 243 bpu.io.in.bits.inMask := mask(if1_npc) 244 bpu.io.out(0).ready := if2_fire 245 bpu.io.out(1).ready := if3_fire 246 bpu.io.out(2).ready := if4_fire 247 bpu.io.predecode.valid := if4_valid 248 bpu.io.predecode.bits.mask := if4_pd.mask 249 bpu.io.predecode.bits.pd := if4_pd.pd 250 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 251 bpu.io.branchInfo.ready := if4_fire 252 253 pd.io.in := io.icacheResp.bits 254 pd.io.prev.valid := if3_hasPrevHalfInstr 255 pd.io.prev.bits := prevHalfInstr.instr 256 // if a fetch packet triggers page fault, set the pf instruction to nop 257 when (!if3_hasPrevHalfInstr && io.icacheResp.bits.ipf) { 258 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 259 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 260 pd.io.in.data := instrs.asUInt 261 }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || io.icacheResp.bits.ipf)) { 262 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 263 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 264 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 265 pd.io.in.data := instrs.asUInt 266 267 when (io.icacheResp.bits.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 268 } 269 270 io.fetchPacket.valid := if4_valid && !io.redirect.valid 271 io.fetchPacket.bits.instrs := if4_pd.instrs 272 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 273 io.fetchPacket.bits.pc := if4_pd.pc 274 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 275 when (if4_bp.taken) { 276 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 277 } 278 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 279 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 280 io.fetchPacket.bits.pd := if4_pd.pd 281 io.fetchPacket.bits.ipf := if4_ipf 282 io.fetchPacket.bits.crossPageIPFFix := if4_crossPageIPF 283 284 // debug info 285 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 286 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 287 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 288 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isFpp:%d isMisPred=%d isReplay=%d pc=%x\n", 289 io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 290 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 291 292 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 293 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 294 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr, crossPageIPF) 295 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr, if4_crossPageIPF) 296 297 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 298 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 299 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 300 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 301 302 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 303 304 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 305 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 306 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 307 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 308 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 309 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr, prevHalfInstr.ipf) 310 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 311 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 312 313 314 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 315 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 316 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 317 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 318 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 319 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n", 320 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix) 321 for (i <- 0 until PredictWidth) { 322 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 323 io.fetchPacket.bits.mask(i), 324 io.fetchPacket.bits.instrs(i), 325 io.fetchPacket.bits.pc(i), 326 io.fetchPacket.bits.pnpc(i), 327 io.fetchPacket.bits.pd(i).isRVC, 328 io.fetchPacket.bits.pd(i).brType, 329 io.fetchPacket.bits.pd(i).isCall, 330 io.fetchPacket.bits.pd(i).isRet 331 ) 332 } 333}