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Searched refs:mod (Results 1 – 22 of 22) sorted by relevance

/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/
H A DVIMacU.scala100 case (mod, i) =>
101 mod.io.fire := io.in.valid
102 mod.io.info.vm := vm
103 mod.io.info.ma := vma
104 mod.io.info.ta := vta
105 mod.io.info.vlmul := vlmul
106 mod.io.info.vl := srcVConfig.vl
107 mod.io.info.vstart := vstart
108 mod.io.info.uopIdx := vuopIdx
109 mod.io.info.vxrm := vxrm
[all …]
H A DVFMA.scala58 case (mod, i) =>
59 mod.io.fire := io.in.valid
60 mod.io.fp_a := vs2Split.io.outVec64b(i)
61 mod.io.fp_b := vs1Split.io.outVec64b(i)
62 mod.io.fp_c := oldVdSplit.io.outVec64b(i)
63 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i))
64 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i))
65 mod.io.frs1 := 0.U // already vf -> vv
66 mod.io.is_frs1 := false.B // already vf -> vv
67 mod.io.uop_idx := vuopIdx(0)
[all …]
H A DVFDivSqrt.scala58 case (mod, i) =>
59 mod.io.start_valid_i := io.in.valid
60 mod.io.finish_ready_i := io.out.ready & io.out.valid
61 mod.io.flush_i := thisRobIdx.needFlush(io.flush)
62 mod.io.fp_format_i := vsew
63 mod.io.opa_i := vs2Split.io.outVec64b(i)
64 mod.io.opb_i := vs1Split.io.outVec64b(i)
65 mod.io.frs2_i := 0.U // already vf -> vv
66 mod.io.frs1_i := 0.U // already vf -> vv
67 mod.io.is_frs2_i := false.B // already vf -> vv
[all …]
H A DVIAluFix.scala236 case (mod, i) =>
237 mod.io.fire := io.in.valid
238 mod.io.opcode := opcode
240 mod.io.info.vm := vm
241 mod.io.info.ma := vma
242 mod.io.info.ta := vta
243 mod.io.info.vlmul := vlmul
244 mod.io.info.vl := vl
245 mod.io.info.vstart := vstart
246 mod.io.info.uopIdx := vuopIdx
[all …]
H A DVFALU.scala228 case (mod, i) =>
229 mod.io.fire := io.in.valid
230 mod.io.fp_a := vs2Split.io.outVec64b(i)
231 mod.io.fp_b := vs1Split.io.outVec64b(i)
232 … mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i))
233 … mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i))
234 mod.io.frs1 := 0.U // already vf -> vv
235 mod.io.is_frs1 := false.B // already vf -> vv
236 …mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift,…
237 …mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i =…
[all …]
/XiangShan/src/main/scala/xiangshan/backend/
H A DPipeGroupConnect.scala70 val mod = Module(new PipeGroupConnect(left.size, chiselTypeOf(left.head.bits))) constant
71 mod.io.flush := flush
72 mod.io.in.zipWithIndex.foreach { case (in, i) =>
77 mod.io.outAllFire := rightAllFire
78 right <> mod.io.out
81 mod.suggestName(suggestName)
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/
H A DNewCSR.scala524 miregiprios.foreach { mod =>
525 mod.w.wen := mireg.w.wen && (miselect.regOut.ALL.asUInt === mod.addr.U)
526 mod.w.wdata := wdata
529 siregiprios.foreach { mod =>
530 mod.w.wen := sireg.w.wen && (siselect.regOut.ALL.asUInt === mod.addr.U)
531 mod.w.wdata := wdata
534 iregiprios.foreach { mod =>
535 mod match {
545 pmpcfgs.zipWithIndex.foreach { case (mod, i) =>
546 mod.w.wen := wenLegalReg && (addr === (CSRs.pmpcfg0 + i / 8 * 2).U)
[all …]
H A DDebug.scala61 val mcontrol6WireVec = tdata1Vec.map{ mod => {
63 mcontrol6Wire := mod.DATA.asUInt
112 case (tEnable, mod) => tEnable && mod.isFetchTrigger
115 case (tEnable, mod) => tEnable && mod.isMemAccTrigger
H A DDebugLevel.scala95 tdata1RegVec.zipWithIndex.map{case (mod, idx) => (tselect.rdata === idx.U) -> mod.rdata}
99 tdata2RegVec.zipWithIndex.map{case (mod, idx) => (tselect.rdata === idx.U) -> mod.rdata}
102 debugCSRMods.foreach { mod =>
103 mod match {
H A DCSRPMA.scala50 pmaCSRMods.foreach { mod =>
51 mod match {
H A DCSRPMP.scala56 pmpCSRMods.foreach { mod =>
57 mod match {
H A DCSRAIA.scala191 aiaCSRMods.foreach { mod =>
192 mod match {
H A DVirtualSupervisorLevel.scala239 virtualSupervisorCSRMods.foreach(mod =>
240 …require(mod.addr > 0, s"The address of ${mod.modName} has not been set, you can use setAddr(CSRAdd…
/XiangShan/src/main/scala/xiangshan/backend/issue/
H A DImmExtractor.scala49 val mod = Module(new ImmExtractor(dataBits, immTypeSet)) constant
50 mod.io.in.imm := imm
51 mod.io.in.immType := immType
52 mod.io.out.imm
/XiangShan/src/main/scala/top/
H A DGenerator.scala25 def execute(args: Array[String], mod: => chisel3.RawModule, firtoolOpts: Array[String]) = {
28 (new XiangShanStage).execute(args, ChiselGeneratorAnnotation(() => mod) +: annotations)
H A DXSNoCTop.scala132 val mod = this.toNamed constant
134 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
H A DTop.scala232 val mod = this.toNamed constant
234 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
/XiangShan/src/main/scala/device/standalone/
H A DStandAloneDevice.scala151 val mod = this.toNamed constant
153 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
160 val mod = this.toNamed constant
162 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
/XiangShan/src/main/scala/device/
H A DMemEncryptUtil.scala274 val mod = OneRoundForEncDecs(i) constant
275 mod.io.round_key_in := io.onepipe_in.round_key_in(i)
276 …if (i == 0) mod.io.data_in := io.onepipe_in.data_in else mod.io.data_in := OneRoundForEncDecs(i - …
317 val mod = OneRoundForEncDecs(i) constant
318 mod.io.round_key_in := io.onepipe_in.round_key_in(i)
319 …if (i == 0) mod.io.data_in := io.onepipe_in.data_in else mod.io.data_in := OneRoundForEncDecs(i - …
447 val mod = OneRoundForEncDecs(i) constant
448 mod.io.round_key_in := io.in.round_key_in(i)
449 …if (i == 0) mod.io.data_in := io.in.data_in else mod.io.data_in := OneRoundForEncDecs(i - 1).io.re…
/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala1032 case mod =>
1033 mod.module.io_pseudoError.foreach {
1038 case mod =>
1039 mod.io.pseudo_error.valid := false.B
1040 mod.io.pseudo_error.bits := DontCare
1050 ldu.map(mod => mod.io.pseudo_error <> ctrlUnit.io_pseudoError(0))
/XiangShan/
H A D.gitignore248 *.mod
/XiangShan/src/main/scala/xiangshan/mem/vector/
H A DVecCommon.scala706 def apply(elementMask: UInt, start: UInt, vl: UInt , mod: Boolean): UInt = {
710 if(mod){