Lines Matching refs:mod
524 miregiprios.foreach { mod =>
525 mod.w.wen := mireg.w.wen && (miselect.regOut.ALL.asUInt === mod.addr.U)
526 mod.w.wdata := wdata
529 siregiprios.foreach { mod =>
530 mod.w.wen := sireg.w.wen && (siselect.regOut.ALL.asUInt === mod.addr.U)
531 mod.w.wdata := wdata
534 iregiprios.foreach { mod =>
535 mod match {
545 pmpcfgs.zipWithIndex.foreach { case (mod, i) =>
546 mod.w.wen := wenLegalReg && (addr === (CSRs.pmpcfg0 + i / 8 * 2).U)
547 mod.w.wdata := pmpEntryMod.io.out.pmpCfgWData(8*((i%8)+1)-1,8*(i%8))
550 pmpaddr.zipWithIndex.foreach { case (mod, i) =>
551 mod.w.wen := wenLegalReg && (addr === (CSRs.pmpaddr0 + i).U)
552 mod.w.wdata := pmpEntryMod.io.out.pmpAddrWData(i)
555 pmacfgs.zipWithIndex.foreach { case (mod, i) =>
556 mod.w.wen := wenLegalReg && (addr === (CSRConst.PmacfgBase + i / 8 * 2).U)
557 mod.w.wdata := pmaEntryMod.io.out.pmaCfgWdata(8*((i%8)+1)-1,8*(i%8))
560 csrMods.foreach { mod =>
561 mod match {
566 mod match {
572 mod match {
578 mod match {
583 mod match {
590 mod match {
606 mod match {
611 mod match {
616 mod match {
621 mod match {
626 mod match {
631 mod match {
636 mod match {
641 mod match {
646 mod match {
651 mod match {
656 mod match {
669 mod match {
676 mod match {
681 mod match {
686 mod match {
703 mod match {
708 mod match {
713 mod match {
719 mod match {
740 mod match {
752 mod match {
759 mod match {
766 mod match {
771 mod match {
778 csrMods.foreach { mod =>
780 println(mod.dumpFields)
1140 val tdata1Vec = tdata1RegVec.map{ mod => {
1142 tdata1Wire := mod.rdata