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eca6983f |
| 26-Feb-2025 |
Zehao Liu <[email protected]> |
fix(dbltrp): set sdt to 0 when exe sret to VU (#4313)
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e50a46ea |
| 17-Jan-2025 |
Guanghui Cheng <[email protected]> |
fix(dret): clear xstatus.xDT conditionally when dret is executed (#4193)
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6808b803 |
| 29-Oct-2024 |
Zehao Liu <[email protected]> |
feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)
* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco
feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)
* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)
---
* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN
Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.
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60b1c081 |
| 06-Sep-2024 |
Xuan Hu <[email protected]> |
fix(CSR): typo in vsip.LocalIP's alias condition
* vsip.LocalIP is alias of hvip.LocalIP when !hideleg && hvien not !hideleg && mvien
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3e8a0170 |
| 25-Jul-2024 |
Xuan Hu <[email protected]> |
ROB: clear flushPipe when the enq uop has exception (#3281)
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87e82edd |
| 20-Jul-2024 |
Xiaokun-Pei <[email protected]> |
CSR, RVH: fix the bug about checking vsstatus.vs (#3253)
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499d09b3 |
| 16-Jul-2024 |
sinceforYy <[email protected]> |
NewCSR: set legal init value to WARL Field
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a0231889 |
| 27-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: separate csr modified FS/VS dirty from robCommit.FS/VS dirty
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9c0fd28f |
| 18-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: fix atp CSRs PPN mask
* The writable length of satp is `PAddrBits - PageOffsetWidth`. * The writable length of vsatp varies with hgatp.MODE. * When hgatp.MODE is `Bare`, it's `PAddrBits -
NewCSR: fix atp CSRs PPN mask
* The writable length of satp is `PAddrBits - PageOffsetWidth`. * The writable length of vsatp varies with hgatp.MODE. * When hgatp.MODE is `Bare`, it's `PAddrBits - PageOffsetWidth`. * When hgatp.MODE is `Sv39x4`, it's `41 - PageOffsetWidth`. * The writable length of hgatp is `PAddrBits - PageOffsetWidth`. Since the root page table is 16 KiB and must be aligned to a 16-KiB boundary, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros. * A write to hgatp with an unsupported MODE value is not ignored as it is for satp. * Instead, the fields of hgatp are WARL in the normal way, when so indicated.
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82f438ed |
| 13-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: update vsstatus.FS/VS only in VirtMode
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4d2be3d2 |
| 05-Jun-2024 |
sinceforYy <[email protected]> |
NewCSR: add FS, VS check
* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode * Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode * when sstat
NewCSR: add FS, VS check
* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode * Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode * when sstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in HS/HU mode * when sstatus.FS/VS or vsstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in VS/VU mode * when sstatus.FS/VS or vsstatus.FS/VS is Off, access fp/vec CSR will raise EX_II
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946f0090 |
| 11-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: make M and VS level interrupt bits in sip/sie/vsie/vsip read-only 0
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a2eeddbf |
| 10-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: fix vsie write to alias mie and sie
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8e6494c1 |
| 10-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: fix VS level's interrupt enable and pending bits delegated from HS level
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94895e77 |
| 07-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: fix rdata when VS mode access VS CSRs by address of S mode
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1d192ad8 |
| 02-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: support AIA extension Interrupt Pending and Enable
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1ac4f6b0 |
| 29-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: make vsip.SGEIP and vsie.SGEIE RO
* `SGEIP` should not exist in `vsip` and neither should `SGEIE`. Mark them RO to optimize
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0b4c00ff |
| 29-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: support Sstc extension
* Add `stimecmp` and `vstimecmp` CSR. * Add `STIP` and `VSTIP` interrupt. * Add `STCE` field in `menvcfg` and `henvcfg` to enable Sstc extension.
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f56c6de4 |
| 27-May-2024 |
sinceforYy <[email protected]> |
NewCSR: update vsatp CSR
* Other fields still update when PrivState.V=0 and vsatp.MODE writes illegal value
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a37e0a1f |
| 22-May-2024 |
sinceforYy <[email protected]> |
NewCSR: fix rdataFields and Initialize CSR
* fix mtopi,stopi,vstopi regOut * fix rdataFields :|= regOut * fix pmpcfg regOut * Initialze hie, hip, hedeleg, hideleg * use regOut when field as alias
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8aa89407 |
| 20-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: change the type of rdata to UInt in CSRModule
* Since the rdata bundle is used to get CSR read value, we change the type of rdata to UInt(64.W) and do all needed expansions before the value
NewCSR: change the type of rdata to UInt in CSRModule
* Since the rdata bundle is used to get CSR read value, we change the type of rdata to UInt(64.W) and do all needed expansions before the value assigned to rdata bundles.
show more ...
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f9913d9b |
| 17-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: make satp, vsatp and hgatp unchanged when write with illegal MODE
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8056933d |
| 15-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: make COIE,LPRASEIE,HPRASEIE fields in xie read only
* Todo: set COIE,LPRASEIE,HPRASEIE in mie RW
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760398d7 |
| 13-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: refactor to make better verilog generation
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e877d8bf |
| 11-Apr-2024 |
Xuan Hu <[email protected]> |
NewCSR: add fu wrapper
|