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/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_pwm.h121 …RF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
122 …_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
168 * @brief Type used for defining duty cycle values for a sequence
174 * @brief Structure for defining duty cycle values for a sequence
178 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
179 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
183 * @brief Structure for defining duty cycle values for a sequence
188 uint16_t channel_0; ///< Duty cycle value for channel 0.
189 uint16_t channel_1; ///< Duty cycle value for channel 1.
190 uint16_t channel_2; ///< Duty cycle value for channel 2.
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/AT91SAM7X/
H A Dstart_rvds.S109 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
112 ;// <0=> Read: 1 cycle / Write: 2 cycles
113 ;// <1=> Read: 2 cycle / Write: 3 cycles
114 ;// <2=> Read: 3 cycle / Write: 4 cycles
115 ;// <3=> Read: 4 cycle / Write: 4 cycles
121 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
124 ;// <0=> Read: 1 cycle / Write: 2 cycles
125 ;// <1=> Read: 2 cycle / Write: 3 cycles
126 ;// <2=> Read: 3 cycle / Write: 4 cycles
127 ;// <3=> Read: 4 cycle / Write: 4 cycles
/nrf52832-nimble/rt-thread/libcpu/arm/AT91SAM7S/
H A Dstart_rvds.S106 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
109 ;// <0=> Read: 1 cycle / Write: 2 cycles
110 ;// <1=> Read: 2 cycle / Write: 3 cycles
111 ;// <2=> Read: 3 cycle / Write: 4 cycles
112 ;// <3=> Read: 4 cycle / Write: 4 cycles
118 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
121 ;// <0=> Read: 1 cycle / Write: 2 cycles
122 ;// <1=> Read: 2 cycle / Write: 3 cycles
123 ;// <2=> Read: 3 cycle / Write: 4 cycles
124 ;// <3=> Read: 4 cycle / Write: 4 cycles
/nrf52832-nimble/rt-thread/components/drivers/cputime/
H A Dcputime_cortexm.c17 /* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */
46 /* whether cycle counter not enabled */ in cortexm_cputime_init()
49 /* enable cycle counter */ in cortexm_cputime_init()
/nrf52832-nimble/nordic/nrfx/drivers/include/
H A Dnrfx_pwm.h142 of duty cycle values, this might result in
242 * @note The array containing the duty cycle values for the specified sequence
269 * @note The array containing the duty cycle values for the specified sequence
304 * cycle value for a certain number of PWM periods, the last played value
348 * @brief Function for updating the pointer to the duty cycle values
353 * @param[in] values New pointer to the duty cycle values.
360 * @brief Function for updating the number of duty cycle values
365 * @param[in] length New number of the duty cycle values.
372 * @brief Function for updating the number of repeats for duty cycle values
/nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/
H A Dstart_rvds.S227 ;// <o0.2..3> Tpac: Page Mode Access Cycle
233 ;// <o0.8..10> Tacc: Access Cycle
253 ;// <o1.2..3> Tpac: Page Mode Access Cycle
259 ;// <o1.8..10> Tacc: Access Cycle
279 ;// <o2.2..3> Tpac: Page Mode Access Cycle
285 ;// <o2.8..10> Tacc: Access Cycle
305 ;// <o3.2..3> Tpac: Page Mode Access Cycle
311 ;// <o3.8..10> Tacc: Access Cycle
331 ;// <o4.2..3> Tpac: Page Mode Access Cycle
337 ;// <o4.8..10> Tacc: Access Cycle
[all …]
H A Dcpu.c28 /* flush cycle */ in rt_hw_cpu_icache_enable()
/nrf52832-nimble/rt-thread/libcpu/arm/s3c24x0/
H A Dstart_rvds.S278 ;// <o2.8..10> Tacc: Access Cycle
285 ;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
295 ;// <o3.8..10> Tacc: Access Cycle
302 ;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
312 ;// <o4.8..10> Tacc: Access Cycle
319 ;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
329 ;// <o5.8..10> Tacc: Access Cycle
336 ;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
346 ;// <o6.8..10> Tacc: Access Cycle
353 ;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
[all …]
/nrf52832-nimble/packages/NimBLE-latest/
H A DREADME.md10 - 高速不可连接广播(High Duty Cycle Non-Connectable Advertising)
17 - 低速定向广播(Low Duty Cycle Directed Advertising)
/nrf52832-nimble/rt-thread/libcpu/arm/realview-a8-vmm/
H A Dpmu.h36 /* Cycle counter reset */
38 /* Cycle counter divider */
/nrf52832-nimble/rt-thread/libcpu/arm/cortex-a/
H A Dpmu.h36 /* Cycle counter reset */
38 /* Cycle counter divider */
/nrf52832-nimble/nordic/nrfx/soc/
H A Dnrfx_coredep.h104 // that the cycle counter is enabled. in nrfx_coredep_delay_us()
108 // Store start value of the cycle counter. in nrfx_coredep_delay_us()
/nrf52832-nimble/nordic/nrfx/drivers/src/
H A Dnrfx_clock.c131 // that cycle counter is enabled. in nrfx_clock_anomaly_132()
135 // Store start value of cycle counter. in nrfx_clock_anomaly_132()
/nrf52832-nimble/rt-thread/libcpu/arm/lpc24xx/
H A Dstart_rvds.S500 ;// <2=> Command delayed strategy plus one clock cycle
609 ;// <1=> One CCLK cycle
613 ;// <1=> One CCLK cycle
656 ;// <1=> One CCLK cycle
660 ;// <1=> One CCLK cycle
702 ;// <1=> One CCLK cycle
706 ;// <1=> One CCLK cycle
748 ;// <1=> One CCLK cycle
752 ;// <1=> One CCLK cycle
/nrf52832-nimble/packages/NimBLE-latest/docs/
H A Dindex.rst41 - High Duty Cycle Non-Connectable Advertising
/nrf52832-nimble/rt-thread/components/drivers/
H A DKconfig64 the cycle counter in DWT for CPU time.
/nrf52832-nimble/rt-thread/tools/kconfig-frontends/frontends/mconf/
H A Dmconf.c42 "<N> to remove it. You may also press the <Space Bar> to cycle\n"
67 " Also, the <TAB> and cursor keys will cycle between <Select>,\n"
91 " Also, the <TAB> and cursor keys will cycle between <Select> and\n"
/nrf52832-nimble/packages/NimBLE-latest/apps/blecsc/src/
H A Dblecsc_sens.c308 MSH_CMD_EXPORT_ALIAS(blecsc_sens_entry, blecsc_sens, "bluetooth cycle sensor sample");
/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/src/core/
H A Dmemp.c98 * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm".
/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/src/core/
H A Dmemp.c98 * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm".
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/
H A Dsyscfg.yml207 the help of a reduced scan duty cycle. The downside of this
/nrf52832-nimble/rt-thread/components/net/lwip-1.4.1/src/core/
H A Dmemp.c179 * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm".
/nrf52832-nimble/packages/NimBLE-latest/apps/bletest/src/
H A Dbletest_hci.c433 /* Do not check if high duty-cycle directed */ in bletest_hci_le_set_multi_adv_params()
/nrf52832-nimble/rt-thread/libcpu/mips/common/
H A Dmipsregs.h510 * time accounting with a precission of one cycle. I don't have
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/src/
H A Dble_gap.c1975 /* Zero is the default value for filter policy and high duty cycle */ in ble_gap_adv_params_tx()
2017 /* High duty cycle only allowed for directed advertising. */ in ble_gap_adv_validate()
2024 /* High duty cycle only allowed for directed advertising. */ in ble_gap_adv_validate()
2330 /* Zero is the default value for filter policy and high duty cycle */ in ble_gap_ext_adv_params_tx()

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