xref: /nrf52832-nimble/rt-thread/components/drivers/cputime/cputime_cortexm.c (revision 104654410c56c573564690304ae786df310c91fc) 
1*10465441SEvalZero /*
2*10465441SEvalZero  * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero  *
4*10465441SEvalZero  * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero  *
6*10465441SEvalZero  * Change Logs:
7*10465441SEvalZero  * Date           Author            Notes
8*10465441SEvalZero  * 2017-12-23     Bernard           first version
9*10465441SEvalZero  */
10*10465441SEvalZero 
11*10465441SEvalZero #include <rthw.h>
12*10465441SEvalZero #include <rtdevice.h>
13*10465441SEvalZero #include <rtthread.h>
14*10465441SEvalZero 
15*10465441SEvalZero #include <board.h>
16*10465441SEvalZero 
17*10465441SEvalZero /* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */
18*10465441SEvalZero 
cortexm_cputime_getres(void)19*10465441SEvalZero static float cortexm_cputime_getres(void)
20*10465441SEvalZero {
21*10465441SEvalZero     float ret = 1000 * 1000 * 1000;
22*10465441SEvalZero 
23*10465441SEvalZero     ret = ret / SystemCoreClock;
24*10465441SEvalZero     return ret;
25*10465441SEvalZero }
26*10465441SEvalZero 
cortexm_cputime_gettime(void)27*10465441SEvalZero static uint32_t cortexm_cputime_gettime(void)
28*10465441SEvalZero {
29*10465441SEvalZero     return DWT->CYCCNT;
30*10465441SEvalZero }
31*10465441SEvalZero 
32*10465441SEvalZero const static struct rt_clock_cputime_ops _cortexm_ops =
33*10465441SEvalZero {
34*10465441SEvalZero     cortexm_cputime_getres,
35*10465441SEvalZero     cortexm_cputime_gettime
36*10465441SEvalZero };
37*10465441SEvalZero 
cortexm_cputime_init(void)38*10465441SEvalZero int cortexm_cputime_init(void)
39*10465441SEvalZero {
40*10465441SEvalZero     /* check support bit */
41*10465441SEvalZero     if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0)
42*10465441SEvalZero     {
43*10465441SEvalZero         /* enable trace*/
44*10465441SEvalZero         CoreDebug->DEMCR |= (1UL << CoreDebug_DEMCR_TRCENA_Pos);
45*10465441SEvalZero 
46*10465441SEvalZero         /* whether cycle counter not enabled */
47*10465441SEvalZero         if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0)
48*10465441SEvalZero         {
49*10465441SEvalZero             /* enable cycle counter */
50*10465441SEvalZero             DWT->CTRL |= (1UL << DWT_CTRL_CYCCNTENA_Pos);
51*10465441SEvalZero         }
52*10465441SEvalZero 
53*10465441SEvalZero         clock_cpu_setops(&_cortexm_ops);
54*10465441SEvalZero     }
55*10465441SEvalZero 
56*10465441SEvalZero     return 0;
57*10465441SEvalZero }
58*10465441SEvalZero INIT_BOARD_EXPORT(cortexm_cputime_init);
59