Lines Matching full:cycle
278 ;// <o2.8..10> Tacc: Access Cycle
285 ;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
295 ;// <o3.8..10> Tacc: Access Cycle
302 ;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
312 ;// <o4.8..10> Tacc: Access Cycle
319 ;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
329 ;// <o5.8..10> Tacc: Access Cycle
336 ;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
346 ;// <o6.8..10> Tacc: Access Cycle
353 ;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
363 ;// <o7.8..10> Tacc: Access Cycle
370 ;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode
382 ;// <o8.8..10> Tacc: Access Cycle
389 ;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
405 ;// <o9.8..10> Tacc: Access Cycle
412 ;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
427 ;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time
428 ;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp
436 ;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle