fix: add low power related logic (#4554)

refactor(DFT): refactor `DFT` IO (#4530)

fix(XSTileWrap): remove useless IMSICAsync (#4515)

Already included in CSR.

feat(AIA): integrate ChiselAIA again (#4509)

chore(XSNoCTop): minor connection changes (#4501)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoo

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoop.
* low-power process is controlled by FSM to follow the steps: flush L2
-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)
* SoC plays as PPU to generate power on/off sequence with signals:
isolation/reset/clock, also the power on/off req/ack signals

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feat(AIA): integrate ChiselAIA (#4378)

feat(dfx): integerate dfx components (#4312)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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feat(DM, hartReset): support `hartReset` which could reset selected harts

* Add hartResetReq in XSNocTop.
* Support `hartReset` features

feat(trace): add TraceCoreInterface in top.

feat(dbltrp) : add support for critical error (#3793)

fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

feat(Synchronizer): use unified AsyncResetSynchronizerShiftReg (#3609)

fix(XSNoCTop): add port `hartIsInReset` for StandAloneDebugModule. (#3538)

SoC, XSNoCTop, XSTileWrap: add switch for the async bridges (#3459)

Top: add XSTileWrap for async signals (#3400)

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: zhaohong1988 <[email protected]>