1/*************************************************************************************** 2* Copyright (c) 2024-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024-2025 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tilelink._ 25import freechips.rocketchip.util._ 26import system.HasSoCParameter 27import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO} 28import utility.sram.SramBroadcastBundle 29import utility.{DFTResetSignals, IntBuffer, ResetGen} 30import xiangshan.backend.trace.TraceCoreInterface 31 32// This module is used for XSNoCTop for async time domain and divide different 33// voltage domain. Everything in this module should be in the core clock domain 34// and higher voltage domain. 35class XSTileWrap()(implicit p: Parameters) extends LazyModule 36 with HasXSParameter 37 with HasSoCParameter 38{ 39 override def shouldBeInlined: Boolean = false 40 41 val tile = LazyModule(new XSTile()) 42 43 // interrupts sync 44 val clintIntNode = IntIdentityNode() 45 val debugIntNode = IntIdentityNode() 46 val plicIntNode = IntIdentityNode() 47 val beuIntNode = IntIdentityNode() 48 val nmiIntNode = IntIdentityNode() 49 tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode 50 tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode 51 tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode 52 tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode 53 beuIntNode := IntBuffer() := tile.beu_int_source 54 55 // seperate TL bus 56 println(s"SeperateTLBus = $SeperateTLBus") 57 println(s"EnableSeperateTLAsync = $EnableSeperateTLAsync") 58 // asynchronous bridge source node 59 val tlAsyncSourceOpt = Option.when(SeperateTLBus && EnableSeperateTLAsync)(LazyModule(new TLAsyncCrossingSource())) 60 tlAsyncSourceOpt.foreach(_.node := tile.sep_tl_opt.get) 61 // synchronous source node 62 val tlSyncSourceOpt = Option.when(SeperateTLBus && !EnableSeperateTLAsync)(TLTempNode()) 63 tlSyncSourceOpt.foreach(_ := tile.sep_tl_opt.get) 64 65 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) { 66 val clock = IO(Input(Clock())) 67 val reset = IO(Input(AsyncReset())) 68 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset()))) 69 val soc_reset = IO(Input(AsyncReset())) 70 val io = IO(new Bundle { 71 val hartId = Input(UInt(hartIdLen.W)) 72 val msiInfo = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W))) 73 val msiAck = Output(Bool()) 74 val reset_vector = Input(UInt(PAddrBits.W)) 75 val cpu_halt = Output(Bool()) 76 val cpu_crtical_error = Output(Bool()) 77 val hartResetReq = Input(Bool()) 78 val hartIsInReset = Output(Bool()) 79 val traceCoreInterface = new TraceCoreInterface 80 val debugTopDown = new Bundle { 81 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 82 val l3MissMatch = Input(Bool()) 83 } 84 val l3Miss = Input(Bool()) 85 val chi = EnableCHIAsyncBridge match { 86 case Some(param) => new AsyncPortIO(param) 87 case None => new PortIO 88 } 89 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 90 val clintTime = EnableClintAsyncBridge match { 91 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param)) 92 case None => Input(ValidIO(UInt(64.W))) 93 } 94 val dft = Option.when(hasDFT)(Input(new SramBroadcastBundle)) 95 val dft_reset = Option.when(hasMbist)(Input(new DFTResetSignals())) 96 val l2_flush_en = Option.when(EnablePowerDown) (Output(Bool())) 97 val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool())) 98 val pwrdown_req_n = Option.when(EnablePowerDown) (Input (Bool())) 99 val pwrdown_ack_n = Option.when(EnablePowerDown) (Output (Bool())) 100 val iso_en = Option.when(EnablePowerDown) (Input (Bool())) 101 }) 102 103 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(2, io.dft_reset)) 104 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(2, io.dft_reset))) 105 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(2, io.dft_reset)) 106 107 // override LazyRawModuleImp's clock and reset 108 childClock := clock 109 childReset := reset_sync 110 111 tile.module.io.hartId := io.hartId 112 tile.module.io.msiInfo := io.msiInfo 113 tile.module.io.reset_vector := io.reset_vector 114 tile.module.io.dft.zip(io.dft).foreach({ case (a, b) => a := b }) 115 tile.module.io.dft_reset.zip(io.dft_reset).foreach({ case (a, b) => a := b }) 116 io.cpu_halt := tile.module.io.cpu_halt 117 io.cpu_crtical_error := tile.module.io.cpu_crtical_error 118 io.msiAck := tile.module.io.msiAck 119 io.hartIsInReset := tile.module.io.hartIsInReset 120 io.traceCoreInterface <> tile.module.io.traceCoreInterface 121 io.debugTopDown <> tile.module.io.debugTopDown 122 tile.module.io.l3Miss := io.l3Miss 123 tile.module.io.nodeID.foreach(_ := io.nodeID.get) 124 io.l2_flush_en.foreach { _ := tile.module.io.l2_flush_en.getOrElse(false.B) } 125 io.l2_flush_done.foreach { _ := tile.module.io.l2_flush_done.getOrElse(false.B) } 126 io.pwrdown_ack_n.foreach { _ := true.B } 127 128 // CLINT Async Queue Sink 129 EnableClintAsyncBridge match { 130 case Some(param) => 131 val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param))) 132 sink.io.async <> io.clintTime 133 sink.io.deq.ready := true.B 134 tile.module.io.clintTime.valid := sink.io.deq.valid 135 tile.module.io.clintTime.bits := sink.io.deq.bits 136 case None => 137 tile.module.io.clintTime := io.clintTime 138 } 139 140 // CHI Async Queue Source 141 EnableCHIAsyncBridge match { 142 case Some(param) => 143 val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param))) 144 source.io.enq <> tile.module.io.chi.get 145 io.chi <> source.io.async 146 case None => 147 require(enableCHI) 148 io.chi <> tile.module.io.chi.get 149 } 150 151 // Seperate DebugModule TL Async Queue Source 152 if (SeperateTLBus && EnableSeperateTLAsync) { 153 tlAsyncSourceOpt.get.module.clock := clock 154 tlAsyncSourceOpt.get.module.reset := soc_reset_sync 155 } 156 157 withClockAndReset(clock, reset_sync) { 158 // Modules are reset one by one 159 // reset ----> SYNC --> XSTile 160 val resetChain = Seq(Seq(tile.module)) 161 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform, io.dft_reset) 162 } 163 dontTouch(io.hartId) 164 dontTouch(io.msiInfo) 165 } 166 lazy val module = new XSTileWrapImp(this) 167} 168