feat(isa): add isa-base and isa-extensions to param and dts (#3953)

chore(dts): remove very vague print (#3799)

This line makes the following print, which is not human-readable.

fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input of these modules will go through `ResetGen` and then drives the
reset of the registers inside the module.

<img
src="https://github.com/user-attachments/assets/1f544afe-4644-4604-ba6f-d14d31909f78"
width="50%">

---------
Co-authored-by: chengguanghui <[email protected]>

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MISC: add H-ext to "riscv,isa" of dts

XSTile partition (#2390)

This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock

XSTile partition (#2390)

This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock and all the interfaces from core to tile will go through MemBlock.

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TLB: Modify TLB structure to full-asso with 48 entries (#2289)

* TLB: Modify TLB structure to full-asso with 48 entries

* TLB: Fix wrong changes on XSDts

* TLB: modify signal naming

DTS: add interrupt-controller into cpu (#1298)

Fix multi-core dedup bug (#1235)

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

Refactor cache params (#1078)

l0tlb: add a new level tlb, a load tlb and a store tlb (#961)

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b97230d6fdeedaf4e4905092ade

l0tlb: add a new level tlb, a load tlb and a store tlb (#961)

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b97230d6fdeedaf4e4905092adef6e768b4f.

* fu: remove unused import

* mmu.tlb: 2 load/store pipeline has 1 dtlb

* mmu: remove btlb, the l1-tlb

* mmu: set split-tlb to 32 to check perf effect

* mmu: wrap tlb's param with TLBParameters

* mmu: add params 'useBTlb'

dtlb size is small: normal 8, super 2

* mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding)

* mmu.tlb: seperate tlb's storage, relative hit/sfence logic

tlb now supports full-associate, set-associate, directive-associate.
more: change tlb's parameter usage, change util.Random to support
case that mod is 1.

* mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da)

be carefull to use tlb's parameter, only a part of param combination
is supported

* mmu.tlb: fix bug of hit method and victim write

* mmu.tlb: add tlb storage's perf counter

* mmu.tlb: rewrite replace part, support set or non-set

* mmu.tlb: add param outReplace to receive out replace index

* mmu.tlb: change param superSize to superNWays

add param superNSets, which should always be 1

* mmu.tlb: change some perf counter's name and change some params

* mmu.tlb: fix bug of replace io bundle

* mmu.tlb: remove unused signal wayIdx in tlbstorageio

* mmu.tlb: separate tlb_ld/st into two 'same' tlb

* mmu.tlb: when nWays is 1, replace returns 0.U

before, replace will return 1.U, no influence for refill but bad
for perf counter

* mmu.tlb: give tlb_ld and tlb_st a name (in waveform)

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misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Auto generate dts with diplomacy (#817)

* Update mill and rocket-chip

* [WIP] auto generate dts by diplomacy