xref: /XiangShan/src/main/scala/xiangshan/XSDts.scala (revision afcc4f2af0cacb47e70082c066edb7033f3af072) 
1// See LICENSE.SiFive for license details.
2
3package xiangshan
4
5import freechips.rocketchip.diplomacy._
6
7trait HasXSDts {
8  this: XSCore =>
9
10  val device: SimpleDevice = new SimpleDevice("cpu", Seq("ICT,xiangshan", "riscv")) {
11    override def parent: Some[Device] = Some(ResourceAnchors.cpus)
12
13    def cpuProperties: PropertyMap = Map(
14      "device_type" -> "cpu".asProperty,
15      "status" -> "okay".asProperty,
16      "clock-frequency" -> 0.asProperty,
17      "riscv,isa" -> "rv64imafdc".asProperty,
18      "timebase-frequency" -> 1000000.asProperty
19    )
20
21    def tileProperties: PropertyMap = {
22      val dcache = Map(
23        "d-cache-block-size" -> dcacheParameters.blockBytes.asProperty,
24        "d-cache-sets" -> dcacheParameters.nSets.asProperty,
25        "d-cache-size" -> (dcacheParameters.nSets * dcacheParameters.nWays * dcacheParameters.blockBytes).asProperty
26      )
27
28      val icache = Map(
29        "i-cache-block-size" -> icacheParameters.blockBytes.asProperty,
30        "i-cache-sets" -> icacheParameters.nSets.asProperty,
31        "i-cache-size" -> (icacheParameters.nSets * icacheParameters.nWays * icacheParameters.blockBytes).asProperty
32      )
33
34      val dtlb = Map(
35        "d-tlb-size" -> TlbEntrySize.asProperty,
36        "d-tlb-sets" -> 1.asProperty
37      )
38
39      val itlb = Map(
40        "i-tlb-size" -> TlbEntrySize.asProperty,
41        "i-tlb-sets" -> 1.asProperty
42      )
43
44      val mmu = Map(
45        "tlb-split" -> Nil,
46        "mmu-type" -> s"riscv,sv$VAddrBits".asProperty
47      )
48
49      val pmp = Nil
50
51      dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp
52    }
53
54    def nextLevelCacheProperty: PropertyOption = {
55      println(memBlock)
56      val outer = memBlock.dcache.clientNode.edges.out.flatMap(_.manager.managers)
57        .filter(_.supportsAcquireB)
58        .flatMap(_.resources.headOption)
59        .map(_.owner.label)
60        .distinct
61      if (outer.isEmpty) None
62      else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
63    }
64
65    override def describe(resources: ResourceBindings): Description = {
66      val Description(name, mapping) = super.describe(resources)
67      Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties)
68    }
69  }
70  ResourceBinding {
71    Resource(device, "reg").bind(ResourceAddress(hardId))
72  }
73}
74