timing(IssueQueue): change mem iq enqNum from 2 to 1 for fix timing and better performance

Remove `RVA23` prefix and enable CMO by default (#3431)

+ Remove `RVA23` prefix to clean up code
+ set `hasCMO` to true by default

PTW, RVH: add the sv48 high gpaddr check (#3427)

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
-

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
- bug fixes
- timing fixes
- SRAM-Queue | https://github.com/OpenXiangShan/CoupledL2/pull/228
- data SRAM splitted into 4 |
https://github.com/OpenXiangShan/CoupledL2/pull/229

---------

Co-authored-by: lixin <[email protected]>

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Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, w

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, which need be collected by the trace.
Therefore, I have also included the trace interface in this PR.

The specific changes are as follows:
* When rob commit, update the ftqIdx and ftqOffset to correctly notify
the frontend which instructions have been committed.
* In each robentry, the ftqIdx and ftqOffset belong to the first
instruction that was compressed, that is Necessary when exceptions
happen.
* Add trace Interface in hart.
* Add trace parameter in parameter.scala.
* Collect trace infomation in backend pipeline.

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MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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Top: add XSTileWrap for async signals (#3400)

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: zhaohong1988 <[email protected]>

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

Parameters: reduce the number of read ports in int register file to 11

Parameters: add parameters for reg cache

Backend: remove load to fp wakeup for fix timing (#3287)

parameters: move CsrCfg, FenceCfg to BJU3 and set latency is UncertainLatency

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits -

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits - PageOffsetWidth`.
* When hgatp.MODE is `Sv39x4`, it's `41 - PageOffsetWidth`.
* The writable length of hgatp is `PAddrBits - PageOffsetWidth`. Since the root page table is 16 KiB and must be aligned to a 16-KiB boundary, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros.
* A write to hgatp with an unsupported MODE value is not ignored as it is for satp.
* Instead, the fields of hgatp are WARL in the normal way, when so indicated.

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NewCSR: add CSR events

ftq: fix redirectReadStart with IfuRedirectNum (#3199)

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
w

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
widths of all read/write ports were set to 6, which works well but is
not parameterized. Now these widths are modified to be controlled by
parameters.

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backend: remove vector wakeup for fix timing (#3145)

Dispatch2Iq: fix timing problem caused by bit width in 'Dispatch2iq'.

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector i

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector instructions other than 'unit-stride' can only be issued on the first port.
Scalars and 'unit-stride' instruction can be emitted at either port if the 'Lsq' allows allocation.

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VLSU: remove splitBuffer for timing

This commit remove SplitBuffer for better timing. The function of SplitBuffer is only used to store unsplit UOPs, and deletion has little impact.

ECC: physically disable tag ecc

FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997)