1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.{max, min} 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HSXLEN: Int = 64, 63 HasMExtension: Boolean = true, 64 HasCExtension: Boolean = true, 65 HasHExtension: Boolean = true, 66 HasDiv: Boolean = true, 67 HasICache: Boolean = true, 68 HasDCache: Boolean = true, 69 AddrBits: Int = 64, 70 VAddrBits: Int = 48, 71 GPAddrBits: Int = 50, 72 HasFPU: Boolean = true, 73 HasVPU: Boolean = true, 74 HasCustomCSRCacheOp: Boolean = true, 75 FetchWidth: Int = 8, 76 AsidLength: Int = 16, 77 VmidLength: Int = 14, 78 EnableBPU: Boolean = true, 79 EnableBPD: Boolean = true, 80 EnableRAS: Boolean = true, 81 EnableLB: Boolean = false, 82 EnableLoop: Boolean = true, 83 EnableSC: Boolean = true, 84 EnbaleTlbDebug: Boolean = false, 85 EnableClockGate: Boolean = true, 86 EnableJal: Boolean = false, 87 EnableFauFTB: Boolean = true, 88 EnableSv48: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 129 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 130 131 uftb.io.in.bits.resp_in(0) := resp_in 132 tage.io.in.bits.resp_in(0) := uftb.io.out 133 ftb.io.in.bits.resp_in(0) := tage.io.out 134 ittage.io.in.bits.resp_in(0) := ftb.io.out 135 ras.io.in.bits.resp_in(0) := ittage.io.out 136 137 (preds, ras.io.out) 138 }, 139 ICacheForceMetaECCError: Boolean = false, 140 ICacheForceDataECCError: Boolean = false, 141 IBufSize: Int = 48, 142 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 143 DecodeWidth: Int = 6, 144 RenameWidth: Int = 6, 145 CommitWidth: Int = 8, 146 RobCommitWidth: Int = 8, 147 RabCommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 155 VecLogicRegs: Int = 32 + 15, // 15: tmp 156 V0LogicRegs: Int = 1, // V0 157 VlLogicRegs: Int = 1, // Vl 158 V0_IDX: Int = 0, 159 Vl_IDX: Int = 0, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 VecDqDeqWidth = 6, 184 LsDqDeqWidth = 6, 185 ), 186 intPreg: PregParams = IntPregParams( 187 numEntries = 224, 188 numRead = None, 189 numWrite = None, 190 ), 191 fpPreg: PregParams = FpPregParams( 192 numEntries = 192, 193 numRead = None, 194 numWrite = None, 195 ), 196 vfPreg: VfPregParams = VfPregParams( 197 numEntries = 128, 198 numRead = None, 199 numWrite = None, 200 ), 201 v0Preg: V0PregParams = V0PregParams( 202 numEntries = 22, 203 numRead = None, 204 numWrite = None, 205 ), 206 vlPreg: VlPregParams = VlPregParams( 207 numEntries = 32, 208 numRead = None, 209 numWrite = None, 210 ), 211 IntRegCacheSize: Int = 16, 212 MemRegCacheSize: Int = 12, 213 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 214 IfuRedirectNum: Int = 1, 215 LoadPipelineWidth: Int = 3, 216 StorePipelineWidth: Int = 2, 217 VecLoadPipelineWidth: Int = 2, 218 VecStorePipelineWidth: Int = 2, 219 VecMemSrcInWidth: Int = 2, 220 VecMemInstWbWidth: Int = 1, 221 VecMemDispatchWidth: Int = 1, 222 VecMemDispatchMaxNumber: Int = 16, 223 VecMemUnitStrideMaxFlowNum: Int = 2, 224 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 225 StoreBufferSize: Int = 16, 226 StoreBufferThreshold: Int = 7, 227 EnsbufferWidth: Int = 2, 228 LoadDependencyWidth: Int = 2, 229 // ============ VLSU ============ 230 VlMergeBufferSize: Int = 16, 231 VsMergeBufferSize: Int = 16, 232 UopWritebackWidth: Int = 2, 233 VLUopWritebackWidth: Int = 2, 234 VSUopWritebackWidth: Int = 1, 235 VSegmentBufferSize: Int = 8, 236 // ============================== 237 UncacheBufferSize: Int = 4, 238 EnableLoadToLoadForward: Boolean = false, 239 EnableFastForward: Boolean = true, 240 EnableLdVioCheckAfterReset: Boolean = true, 241 EnableSoftPrefetchAfterReset: Boolean = true, 242 EnableCacheErrorAfterReset: Boolean = true, 243 EnableAccurateLoadError: Boolean = false, 244 EnableUncacheWriteOutstanding: Boolean = false, 245 EnableStorePrefetchAtIssue: Boolean = false, 246 EnableStorePrefetchAtCommit: Boolean = false, 247 EnableAtCommitMissTrigger: Boolean = true, 248 EnableStorePrefetchSMS: Boolean = false, 249 EnableStorePrefetchSPB: Boolean = false, 250 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 251 MMUVmidLen: Int = 14, 252 ReSelectLen: Int = 7, // load replay queue replay select counter len 253 iwpuParameters: WPUParameters = WPUParameters( 254 enWPU = false, 255 algoName = "mmru", 256 isICache = true, 257 ), 258 dwpuParameters: WPUParameters = WPUParameters( 259 enWPU = false, 260 algoName = "mmru", 261 enCfPred = false, 262 isICache = false, 263 ), 264 itlbParameters: TLBParameters = TLBParameters( 265 name = "itlb", 266 fetchi = true, 267 useDmode = false, 268 NWays = 48, 269 ), 270 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 271 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 272 ldtlbParameters: TLBParameters = TLBParameters( 273 name = "ldtlb", 274 NWays = 48, 275 outReplace = false, 276 partialStaticPMP = true, 277 outsideRecvFlush = true, 278 saveLevel = false, 279 lgMaxSize = 4 280 ), 281 sttlbParameters: TLBParameters = TLBParameters( 282 name = "sttlb", 283 NWays = 48, 284 outReplace = false, 285 partialStaticPMP = true, 286 outsideRecvFlush = true, 287 saveLevel = false, 288 lgMaxSize = 4 289 ), 290 hytlbParameters: TLBParameters = TLBParameters( 291 name = "hytlb", 292 NWays = 48, 293 outReplace = false, 294 partialStaticPMP = true, 295 outsideRecvFlush = true, 296 saveLevel = false, 297 lgMaxSize = 4 298 ), 299 pftlbParameters: TLBParameters = TLBParameters( 300 name = "pftlb", 301 NWays = 48, 302 outReplace = false, 303 partialStaticPMP = true, 304 outsideRecvFlush = true, 305 saveLevel = false, 306 lgMaxSize = 4 307 ), 308 l2ToL1tlbParameters: TLBParameters = TLBParameters( 309 name = "l2tlb", 310 NWays = 48, 311 outReplace = false, 312 partialStaticPMP = true, 313 outsideRecvFlush = true, 314 saveLevel = false 315 ), 316 refillBothTlb: Boolean = false, 317 btlbParameters: TLBParameters = TLBParameters( 318 name = "btlb", 319 NWays = 48, 320 ), 321 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 322 NumPerfCounters: Int = 16, 323 icacheParameters: ICacheParameters = ICacheParameters( 324 tagECC = Some("parity"), 325 dataECC = Some("parity"), 326 replacer = Some("setplru"), 327 ), 328 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 329 tagECC = Some("secded"), 330 dataECC = Some("secded"), 331 replacer = Some("setplru"), 332 nMissEntries = 16, 333 nProbeEntries = 8, 334 nReleaseEntries = 18, 335 nMaxPrefetchEntry = 6, 336 )), 337 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 338 name = "l2", 339 ways = 8, 340 sets = 1024, // default 512KB L2 341 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 342 coupledL2.prefetch.TPParameters()), 343 )), 344 L2NBanks: Int = 1, 345 usePTWRepeater: Boolean = false, 346 softTLB: Boolean = false, // dpi-c l1tlb debug only 347 softPTW: Boolean = false, // dpi-c l2tlb debug only 348 softPTWDelay: Int = 1 349){ 350 def vlWidth = log2Up(VLEN) + 1 351 352 /** 353 * the minimum element length of vector elements 354 */ 355 val minVecElen: Int = 8 356 357 /** 358 * the maximum number of elements in vector register 359 */ 360 val maxElemPerVreg: Int = VLEN / minVecElen 361 362 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 363 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 364 365 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 366 val RegCacheIdxWidth = log2Up(RegCacheSize) 367 368 val intSchdParams = { 369 implicit val schdType: SchedulerType = IntScheduler() 370 SchdBlockParams(Seq( 371 IssueBlockParams(Seq( 372 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 373 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 374 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 375 IssueBlockParams(Seq( 376 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 377 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 378 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 379 IssueBlockParams(Seq( 380 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 381 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 382 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 383 IssueBlockParams(Seq( 384 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 385 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 386 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 387 ), 388 numPregs = intPreg.numEntries, 389 numDeqOutside = 0, 390 schdType = schdType, 391 rfDataWidth = intPreg.dataCfg.dataWidth, 392 numUopIn = dpParams.IntDqDeqWidth, 393 ) 394 } 395 396 val fpSchdParams = { 397 implicit val schdType: SchedulerType = FpScheduler() 398 SchdBlockParams(Seq( 399 IssueBlockParams(Seq( 400 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 401 ), numEntries = 18, numEnq = 2, numComp = 16), 402 IssueBlockParams(Seq( 403 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 IssueBlockParams(Seq( 409 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 410 ), numEntries = 18, numEnq = 2, numComp = 16), 411 IssueBlockParams(Seq( 412 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 413 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 414 ), numEntries = 18, numEnq = 2, numComp = 16), 415 ), 416 numPregs = fpPreg.numEntries, 417 numDeqOutside = 0, 418 schdType = schdType, 419 rfDataWidth = fpPreg.dataCfg.dataWidth, 420 numUopIn = dpParams.VecDqDeqWidth, 421 ) 422 } 423 424 val vfSchdParams = { 425 implicit val schdType: SchedulerType = VfScheduler() 426 SchdBlockParams(Seq( 427 IssueBlockParams(Seq( 428 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 429 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 430 ), numEntries = 16, numEnq = 2, numComp = 14), 431 IssueBlockParams(Seq( 432 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 433 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 434 ), numEntries = 16, numEnq = 2, numComp = 14), 435 IssueBlockParams(Seq( 436 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 437 ), numEntries = 10, numEnq = 2, numComp = 8), 438 ), 439 numPregs = vfPreg.numEntries, 440 numDeqOutside = 0, 441 schdType = schdType, 442 rfDataWidth = vfPreg.dataCfg.dataWidth, 443 numUopIn = dpParams.VecDqDeqWidth, 444 ) 445 } 446 447 val memSchdParams = { 448 implicit val schdType: SchedulerType = MemScheduler() 449 val rfDataWidth = 64 450 451 SchdBlockParams(Seq( 452 IssueBlockParams(Seq( 453 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 454 ), numEntries = 16, numEnq = 2, numComp = 14), 455 IssueBlockParams(Seq( 456 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 457 ), numEntries = 16, numEnq = 2, numComp = 14), 458 IssueBlockParams(Seq( 459 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 IssueBlockParams(Seq( 474 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 475 ), numEntries = 16, numEnq = 2, numComp = 14), 476 IssueBlockParams(Seq( 477 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 478 ), numEntries = 16, numEnq = 2, numComp = 14), 479 ), 480 numPregs = intPreg.numEntries max vfPreg.numEntries, 481 numDeqOutside = 0, 482 schdType = schdType, 483 rfDataWidth = rfDataWidth, 484 numUopIn = dpParams.LsDqDeqWidth, 485 ) 486 } 487 488 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 489 490 def iqWakeUpParams = { 491 Seq( 492 WakeUpConfig( 493 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 494 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 495 ), 496 // TODO: add load -> fp slow wakeup 497 WakeUpConfig( 498 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 499 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 500 ), 501 WakeUpConfig( 502 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 503 Seq("STD0", "STD1") 504 ), 505// WakeUpConfig( 506// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 507// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 508// ), 509 ).flatten 510 } 511 512 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 513 514 val backendParams: BackendParams = backend.BackendParams( 515 Map( 516 IntScheduler() -> intSchdParams, 517 FpScheduler() -> fpSchdParams, 518 VfScheduler() -> vfSchdParams, 519 MemScheduler() -> memSchdParams, 520 ), 521 Seq( 522 intPreg, 523 fpPreg, 524 vfPreg, 525 v0Preg, 526 vlPreg, 527 fakeIntPreg 528 ), 529 iqWakeUpParams, 530 ) 531} 532 533case object DebugOptionsKey extends Field[DebugOptions] 534 535case class DebugOptions 536( 537 FPGAPlatform: Boolean = false, 538 ResetGen: Boolean = false, 539 EnableDifftest: Boolean = false, 540 AlwaysBasicDiff: Boolean = true, 541 EnableDebug: Boolean = false, 542 EnablePerfDebug: Boolean = true, 543 UseDRAMSim: Boolean = false, 544 EnableConstantin: Boolean = false, 545 EnableChiselDB: Boolean = false, 546 AlwaysBasicDB: Boolean = true, 547 EnableRollingDB: Boolean = false 548) 549 550trait HasXSParameter { 551 552 implicit val p: Parameters 553 554 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 555 final val PageOffsetWidth = 12 556 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 557 558 def coreParams = p(XSCoreParamsKey) 559 def env = p(DebugOptionsKey) 560 561 def XLEN = coreParams.XLEN 562 def VLEN = coreParams.VLEN 563 def ELEN = coreParams.ELEN 564 def HSXLEN = coreParams.HSXLEN 565 val minFLen = 32 566 val fLen = 64 567 def hartIdLen = p(MaxHartIdBits) 568 val xLen = XLEN 569 570 def HasMExtension = coreParams.HasMExtension 571 def HasCExtension = coreParams.HasCExtension 572 def HasHExtension = coreParams.HasHExtension 573 def EnableSv48 = coreParams.EnableSv48 574 def HasDiv = coreParams.HasDiv 575 def HasIcache = coreParams.HasICache 576 def HasDcache = coreParams.HasDCache 577 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 578 def GPAddrBits = coreParams.GPAddrBits 579 def VAddrBits = { 580 if (HasHExtension) { 581 coreParams.GPAddrBits 582 } else { 583 coreParams.VAddrBits 584 } 585 } // VAddrBits is Virtual Memory addr bits 586 require(PAddrBits == 48 || !EnableSv48) // Paddr bits should be 48 when Sv48 enable 587 588 def VAddrMaxBits = coreParams.VAddrBits max coreParams.GPAddrBits 589 590 def AsidLength = coreParams.AsidLength 591 def VmidLength = coreParams.VmidLength 592 def ReSelectLen = coreParams.ReSelectLen 593 def AddrBytes = AddrBits / 8 // unused 594 def DataBits = XLEN 595 def DataBytes = DataBits / 8 596 def VDataBytes = VLEN / 8 597 def HasFPU = coreParams.HasFPU 598 def HasVPU = coreParams.HasVPU 599 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 600 def FetchWidth = coreParams.FetchWidth 601 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 602 def EnableBPU = coreParams.EnableBPU 603 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 604 def EnableRAS = coreParams.EnableRAS 605 def EnableLB = coreParams.EnableLB 606 def EnableLoop = coreParams.EnableLoop 607 def EnableSC = coreParams.EnableSC 608 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 609 def HistoryLength = coreParams.HistoryLength 610 def EnableGHistDiff = coreParams.EnableGHistDiff 611 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 612 def EnableClockGate = coreParams.EnableClockGate 613 def UbtbGHRLength = coreParams.UbtbGHRLength 614 def UbtbSize = coreParams.UbtbSize 615 def EnableFauFTB = coreParams.EnableFauFTB 616 def FtbSize = coreParams.FtbSize 617 def FtbWays = coreParams.FtbWays 618 def RasSize = coreParams.RasSize 619 def RasSpecSize = coreParams.RasSpecSize 620 def RasCtrSize = coreParams.RasCtrSize 621 622 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 623 coreParams.branchPredictor(resp_in, p) 624 } 625 def numBr = coreParams.numBr 626 def TageTableInfos = coreParams.TageTableInfos 627 def TageBanks = coreParams.numBr 628 def SCNRows = coreParams.SCNRows 629 def SCCtrBits = coreParams.SCCtrBits 630 def SCHistLens = coreParams.SCHistLens 631 def SCNTables = coreParams.SCNTables 632 633 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 634 case ((n, cb), h) => (n, cb, h) 635 } 636 def ITTageTableInfos = coreParams.ITTageTableInfos 637 type FoldedHistoryInfo = Tuple2[Int, Int] 638 def foldedGHistInfos = 639 (TageTableInfos.map{ case (nRows, h, t) => 640 if (h > 0) 641 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 642 else 643 Set[FoldedHistoryInfo]() 644 }.reduce(_++_).toSet ++ 645 SCTableInfos.map{ case (nRows, _, h) => 646 if (h > 0) 647 Set((h, min(log2Ceil(nRows/TageBanks), h))) 648 else 649 Set[FoldedHistoryInfo]() 650 }.reduce(_++_).toSet ++ 651 ITTageTableInfos.map{ case (nRows, h, t) => 652 if (h > 0) 653 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 654 else 655 Set[FoldedHistoryInfo]() 656 }.reduce(_++_) ++ 657 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 658 ).toList 659 660 661 662 def CacheLineSize = coreParams.CacheLineSize 663 def CacheLineHalfWord = CacheLineSize / 16 664 def ExtHistoryLength = HistoryLength + 64 665 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 666 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 667 def IBufSize = coreParams.IBufSize 668 def IBufNBank = coreParams.IBufNBank 669 def backendParams: BackendParams = coreParams.backendParams 670 def DecodeWidth = coreParams.DecodeWidth 671 def RenameWidth = coreParams.RenameWidth 672 def CommitWidth = coreParams.CommitWidth 673 def RobCommitWidth = coreParams.RobCommitWidth 674 def RabCommitWidth = coreParams.RabCommitWidth 675 def MaxUopSize = coreParams.MaxUopSize 676 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 677 def RenameSnapshotNum = coreParams.RenameSnapshotNum 678 def FtqSize = coreParams.FtqSize 679 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 680 def IntLogicRegs = coreParams.IntLogicRegs 681 def FpLogicRegs = coreParams.FpLogicRegs 682 def VecLogicRegs = coreParams.VecLogicRegs 683 def V0LogicRegs = coreParams.V0LogicRegs 684 def VlLogicRegs = coreParams.VlLogicRegs 685 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 686 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 687 def V0_IDX = coreParams.V0_IDX 688 def Vl_IDX = coreParams.Vl_IDX 689 def IntPhyRegs = coreParams.intPreg.numEntries 690 def FpPhyRegs = coreParams.fpPreg.numEntries 691 def VfPhyRegs = coreParams.vfPreg.numEntries 692 def V0PhyRegs = coreParams.v0Preg.numEntries 693 def VlPhyRegs = coreParams.vlPreg.numEntries 694 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 695 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 696 def RobSize = coreParams.RobSize 697 def RabSize = coreParams.RabSize 698 def VTypeBufferSize = coreParams.VTypeBufferSize 699 def IntRegCacheSize = coreParams.IntRegCacheSize 700 def MemRegCacheSize = coreParams.MemRegCacheSize 701 def RegCacheSize = coreParams.RegCacheSize 702 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 703 /** 704 * the minimum element length of vector elements 705 */ 706 def minVecElen: Int = coreParams.minVecElen 707 708 /** 709 * the maximum number of elements in vector register 710 */ 711 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 712 713 def IntRefCounterWidth = log2Ceil(RobSize) 714 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 715 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 716 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 717 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 718 def LoadQueueRARSize = coreParams.LoadQueueRARSize 719 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 720 def RollbackGroupSize = coreParams.RollbackGroupSize 721 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 722 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 723 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 724 def StoreQueueSize = coreParams.StoreQueueSize 725 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 726 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 727 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 728 def VlsQueueSize = coreParams.VlsQueueSize 729 def dpParams = coreParams.dpParams 730 731 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 732 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 733 734 def NumRedirect = backendParams.numRedirect 735 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 736 def FtqRedirectAheadNum = NumRedirect 737 def IfuRedirectNum = coreParams.IfuRedirectNum 738 def LoadPipelineWidth = coreParams.LoadPipelineWidth 739 def StorePipelineWidth = coreParams.StorePipelineWidth 740 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 741 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 742 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 743 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 744 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 745 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 746 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 747 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 748 def StoreBufferSize = coreParams.StoreBufferSize 749 def StoreBufferThreshold = coreParams.StoreBufferThreshold 750 def EnsbufferWidth = coreParams.EnsbufferWidth 751 def LoadDependencyWidth = coreParams.LoadDependencyWidth 752 def VlMergeBufferSize = coreParams.VlMergeBufferSize 753 def VsMergeBufferSize = coreParams.VsMergeBufferSize 754 def UopWritebackWidth = coreParams.UopWritebackWidth 755 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 756 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 757 def VSegmentBufferSize = coreParams.VSegmentBufferSize 758 def UncacheBufferSize = coreParams.UncacheBufferSize 759 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 760 def EnableFastForward = coreParams.EnableFastForward 761 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 762 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 763 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 764 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 765 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 766 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 767 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 768 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 769 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 770 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 771 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 772 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 773 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 774 def asidLen = coreParams.MMUAsidLen 775 def vmidLen = coreParams.MMUVmidLen 776 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 777 def refillBothTlb = coreParams.refillBothTlb 778 def iwpuParam = coreParams.iwpuParameters 779 def dwpuParam = coreParams.dwpuParameters 780 def itlbParams = coreParams.itlbParameters 781 def ldtlbParams = coreParams.ldtlbParameters 782 def sttlbParams = coreParams.sttlbParameters 783 def hytlbParams = coreParams.hytlbParameters 784 def pftlbParams = coreParams.pftlbParameters 785 def l2ToL1Params = coreParams.l2ToL1tlbParameters 786 def btlbParams = coreParams.btlbParameters 787 def l2tlbParams = coreParams.l2tlbParameters 788 def NumPerfCounters = coreParams.NumPerfCounters 789 790 def instBytes = if (HasCExtension) 2 else 4 791 def instOffsetBits = log2Ceil(instBytes) 792 793 def icacheParameters = coreParams.icacheParameters 794 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 795 796 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 797 // for constrained LR/SC loop 798 def LRSCCycles = 64 799 // for lr storm 800 def LRSCBackOff = 8 801 802 // cache hierarchy configurations 803 def l1BusDataWidth = 256 804 805 // load violation predict 806 def ResetTimeMax2Pow = 20 //1078576 807 def ResetTimeMin2Pow = 10 //1024 808 // wait table parameters 809 def WaitTableSize = 1024 810 def MemPredPCWidth = log2Up(WaitTableSize) 811 def LWTUse2BitCounter = true 812 // store set parameters 813 def SSITSize = WaitTableSize 814 def LFSTSize = 32 815 def SSIDWidth = log2Up(LFSTSize) 816 def LFSTWidth = 4 817 def StoreSetEnable = true // LWT will be disabled if SS is enabled 818 def LFSTEnable = true 819 820 def PCntIncrStep: Int = 6 821 def numPCntHc: Int = 25 822 def numPCntPtw: Int = 19 823 824 def numCSRPCntFrontend = 8 825 def numCSRPCntCtrl = 8 826 def numCSRPCntLsu = 8 827 def numCSRPCntHc = 5 828 def printEventCoding = true 829 830 // Parameters for Sdtrig extension 831 protected def TriggerNum = 4 832 protected def TriggerChainMaxLength = 2 833} 834