fix(AXI4Memory): fix write request enqueue DRAMSim logic for AXI4Memory (#4611)

fix(XSTileWrap): remove useless IMSICAsync (#4515)

Already included in CSR.

feat(AIA): integrate ChiselAIA again (#4509)

fix(AXI4Memory): remove `AWLEN == 0` Check (#4383)

Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

fix(DM): synchronize the `jtag_reset` in standaloneDM (#4414)

chore: fix several deprecation warning (#4352)

feat(AIA): integrate ChiselAIA (#4378)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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fix(AXI4Memory): fix loss of `r` channel packet (#4176)

Co-authored-by: zhanglinjuan <[email protected]>

fix(DM, SBA): add `TLWidthWidget` for sysbus

fix(device, DebugMoudle): do not use clock with Bool type (#4152)

* gsim can not handle such clocks

style(DebugModule): remove unnecessary `XSDebugModuleParams` (#4155)

It is more straight-forward to use `DebugModuleParams` in `Config.scala`.

feat(DM, hartReset): support `hartReset` which could reset selected harts

* Add hartResetReq in XSNocTop.
* Support `hartReset` features

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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fix(AXI4IntrGenerator): extract wdata according to waddr (#4022)

build: bump mill to 0.12.3 (#3933)

fix(DM): enlarge master node addr width for standalone DM (#3896)

timing(IMSIC): AXI4 output should be buffered (#3757)

fix(IMSIC): add TLBuffer for tilelink IO (#3668)

It is better for Top IO to be register out. Add TLBuffer for TileLink
version of IMSIC.

feat(Synchronizer): use unified AsyncResetSynchronizerShiftReg (#3609)

fix(StandAloneDebugModule): use baseAddr from cmdline (#3608)

feat(IMSIC): change tl source width to 4 (#3529)

fix(DM): remove useless signal `hartResetReq`.

fix(Device): use async reset for standalone devices