Cpl2 Feature: Evict@Refill (#2232)

* bump CPL2: for A miss, choose way when refill, then release

* bump utility: fix chiselDB

* bump CPL2: fix C blocking condition

assertion in Monitor of s

Cpl2 Feature: Evict@Refill (#2232)

* bump CPL2: for A miss, choose way when refill, then release

* bump utility: fix chiselDB

* bump CPL2: fix C blocking condition

assertion in Monitor of s1/s3 set blocking
conflicts with C blocking logic
update C blocking modifications in fix-timing

* bump CPL2: fix occWays in ReqBuf

* bump CPL2: fix multiple bugs

* bump CPL2: fix Get/Hint does not read dir and replace at refill

* bump CoupledL2: fix C&D firing logic for Get

* bump CPL2: fix Get problem

* bump CPL2: fix retry

* tmp: try modify L3 probeack logic to avoid verilator bug

* bump CPL2: fix assertion

* Bump CPL2: probe toB should write probeAckData to DS

* Bump Utility

* Bump HuanCun: use param to fix probeack logic under verilator bug

* scripts: add L2 MainPipe-DB parser.sh and helper.py

* bump CPL2: update to master with Evict@Refill

* bump CPL2: misc - fix connection

* bump CPL2 to master

* scripts: give l2DB parser scripts more decent filename

* bump cpl2

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Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump hua

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

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top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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submodules: track commits on master branch (#1988)

util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

* huancun: version change

* util: update to main

* SimTop: delete unused comment

* constantin: fix bug which reduced emputy map

* code opt: add write api in FileRegisters

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test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argp

test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

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bump huancun (#1897)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

huancun: use huancun of nanhu with Top-Down support (#1811)

Added chisel-db to dump hw data into a database automatically

perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bu

perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun

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util.sram: rm a r/w hazard mux which is not needed. bump huancun (#1571)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump

util.sram: rm a r/w hazard mux which is not needed. bump huancun (#1571)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump huancun

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Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-

Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

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bump huancun

Fix the file extension for inline verilog modules.

Bump rocket-chip (#1502)

bump huancun (#1466)

* bump huancun

* bump huancun

* bump huancun

* Insert 1 buffer betwwen L2 and L3

Co-authored-by: LinJiawei <[email protected]>

bump huancun (#1458)

SoC: remove error_xbar; add more buffers (#1454)

* SoC: remove error_xbar; add more buffers

* Bump huancun

* Misc: set timeout threshold to 10000 cycles

* Bump huancun

Bump huancun (#1446)

Adjusted reset signals (#1441)

* Adjusted reset signals

* Support reset tree

bump huancun (#1425)

bump huancun (#1422)

Connect L2 ecc error to BEU / Connect L3 ecc error to PLIC (#1415)

* l2/l3: Report ecc error to beu or plic

* Bump huancun

* Connect l3 ecc error to plic

bump huancun (#1402)

* bump huancun

* Fix probe BtoB

Co-authored-by: LinJiawei <[email protected]>

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still b

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

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