xref: /XiangShan/src/main/scala/xiangshan/XSTile.scala (revision 1b46b9591920008655d659ac88cd0250db769664) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chipsalliance.rocketchip.config.{Config, Parameters}
21import chisel3.util.{Valid, ValidIO}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import coupledL2.{L2ParamKey, CoupledL2}
27import system.HasSoCParameter
28import top.BusPerfMonitor
29import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger}
30
31class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
32  val ecc_error = Valid(UInt(soc.PAddrBits.W))
33}
34
35class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
36  val icache = new L1BusErrorUnitInfo
37  val dcache = new L1BusErrorUnitInfo
38  val l2 = new L1BusErrorUnitInfo
39
40  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
41    List(
42      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
43      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
44      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
45    )
46}
47
48/**
49  *   XSTileMisc contains every module except Core and L2 Cache
50  */
51class XSTileMisc()(implicit p: Parameters) extends LazyModule
52  with HasXSParameter
53  with HasSoCParameter
54{
55  val l1_xbar = TLXbar()
56  val mmio_xbar = TLXbar()
57  val mmio_port = TLIdentityNode() // to L3
58  val memory_port = TLIdentityNode()
59  val beu = LazyModule(new BusErrorUnit(
60    new XSL1BusErrors(), BusErrorUnitParams(0x38010000)
61  ))
62  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform)
63  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform, stat_latency = true)
64  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB)
65  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
66
67  val i_mmio_port = TLTempNode()
68  val d_mmio_port = TLTempNode()
69
70  misc_l2_pmu := l1d_logger
71  l1_xbar :=* misc_l2_pmu
72
73  l2_binder match {
74    case Some(binder) =>
75      memory_port := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder
76    case None =>
77      memory_port := l1_xbar
78  }
79
80  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
81  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
82  beu.node := TLBuffer.chainNode(1) := mmio_xbar
83  mmio_port := TLBuffer() := mmio_xbar
84
85  lazy val module = new LazyModuleImp(this){
86    val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors)))
87    beu.module.io.errors <> beu_errors
88  }
89}
90
91class XSTile()(implicit p: Parameters) extends LazyModule
92  with HasXSParameter
93  with HasSoCParameter
94{
95  private val core = LazyModule(new XSCore())
96  private val misc = LazyModule(new XSTileMisc())
97  private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
98    LazyModule(new CoupledL2()(new Config((_, _, _) => {
99      case L2ParamKey => l2param.copy(hartIds = Seq(p(XSCoreParamsKey).HartId))
100    })))
101  )
102
103  // public ports
104  val memory_port = misc.memory_port
105  val uncache = misc.mmio_port
106  val clint_int_sink = core.clint_int_sink
107  val plic_int_sink = core.plic_int_sink
108  val debug_int_sink = core.debug_int_sink
109  val beu_int_source = misc.beu.intNode
110  val core_reset_sink = BundleBridgeSink(Some(() => Reset()))
111  val l1d_l2_pmu = BusPerfMonitor(name = "L1d_L2", enable = !debugOpts.FPGAPlatform, stat_latency = true)
112
113  val l1d_to_l2_bufferOpt = coreParams.dcacheParametersOpt.map { _ =>
114    val buffer = LazyModule(new TLBuffer)
115    misc.l1d_logger := buffer.node := l1d_l2_pmu := core.memBlock.dcache.clientNode
116    buffer
117  }
118
119  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
120    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
121    buffers.zipWithIndex.foreach{ case (b, i) => {
122      b.suggestName(s"${n}_${i}")
123    }}
124    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
125    (buffers, node)
126  }
127
128  misc.misc_l2_pmu := TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) := core.frontend.icache.clientNode
129  if (!coreParams.softPTW) {
130    misc.misc_l2_pmu := TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) := core.memBlock.ptw_to_l2_buffer.node
131  }
132
133  l2cache match {
134    case Some(l2) =>
135      misc.l2_binder.get :*= l2.node :*= misc.l1_xbar
136      l2.pf_recv_node.map(recv => {
137        println("Connecting L1 prefetcher to L2!")
138        recv := core.memBlock.pf_sender_opt.get
139      })
140    case None =>
141      val dummyMatch = WireDefault(false.B)
142      ExcitingUtils.addSource(dummyMatch, s"L2MissMatch_${p(XSCoreParamsKey).HartId}", ExcitingUtils.Perf, true)
143  }
144
145  misc.i_mmio_port := core.frontend.instrUncache.clientNode
146  misc.d_mmio_port := core.memBlock.uncache.clientNode
147
148  lazy val module = new LazyModuleImp(this){
149    val io = IO(new Bundle {
150      val hartId = Input(UInt(64.W))
151      val reset_vector = Input(UInt(PAddrBits.W))
152      val cpu_halt = Output(Bool())
153    })
154
155    dontTouch(io.hartId)
156
157    val core_soft_rst = core_reset_sink.in.head._1
158
159    core.module.io.hartId := io.hartId
160    core.module.io.reset_vector := DelayN(io.reset_vector, 5)
161    io.cpu_halt := core.module.io.cpu_halt
162    if (l2cache.isDefined) {
163      // TODO: add perfEvents of L2
164      // core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2)
165    }
166    else {
167      core.module.io.perfEvents <> DontCare
168    }
169
170    misc.module.beu_errors.icache <> core.module.io.beu_errors.icache
171    misc.module.beu_errors.dcache <> core.module.io.beu_errors.dcache
172    if (l2cache.isDefined) {
173      // TODO: add ECC interface of L2
174      // misc.module.beu_errors.l2.ecc_error.valid := l2cache.get.module.io.ecc_error.valid
175      // misc.module.beu_errors.l2.ecc_error.bits := l2cache.get.module.io.ecc_error.bits
176      misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
177      core.module.io.l2_hint.bits.sourceId := l2cache.get.module.io.l2_hint.bits
178      core.module.io.l2_hint.valid := l2cache.get.module.io.l2_hint.valid
179    } else {
180      misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
181      core.module.io.l2_hint.bits.sourceId := DontCare
182      core.module.io.l2_hint.valid := false.B
183    }
184
185    // Modules are reset one by one
186    // io_reset ----
187    //             |
188    //             v
189    // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
190    val resetChain = Seq(
191      Seq(misc.module, core.module) ++
192        l1d_to_l2_bufferOpt.map(_.module) ++
193        l2cache.map(_.module)
194    )
195    ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
196  }
197}
198