debug - OpenGrok history log for /XiangShan/debug

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
5c6da657	24-Aug-2020	jinyue110 <[email protected]>	icache: needlush false when state = s_wait_resp Makefile /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
533601ad	20-Aug-2020	jinyue110 <[email protected]>	icache: deal with flushed mem_req wait for refill finish even flush Makefile /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala
83a08305	20-Aug-2020	jinyue110 <[email protected]>	icache: fix bug that flush didn't change state Now cputest PASS 29/33 /XiangShan/Makefile Makefile /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/AXI4ToAXI4Lite.scala /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTL1toN.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/miscMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
88c04e1b	15-Aug-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-lsu-test Makefile cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala
270f8dc1	15-Aug-2020	Yinan Xu <[email protected]>	Merge pull request #175 from RISCVERS/fix-cputest-sh Re-write cputest.sh to make bash happy cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/scala/top/XSSim.scala
bc146afb	14-Aug-2020	LinJiawei <[email protected]>	Rewrite cputest.sh to make bash happy cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/scala/top/XSSim.scala
3a1c7672	13-Aug-2020	GouLingrui <[email protected]>	Merge branch 'dev-frontend' of https://github.com/RISCVERS/XiangShan into dev-frontend Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala
3d3cb33d	10-Aug-2020	jinyue110 <[email protected]>	RAS: add pop push logic when recover /XiangShan/Makefile /XiangShan/build.sc Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
dc56cdc2	07-Aug-2020	William Wang <[email protected]>	Lsroq: fix load mask cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala
f310abee	06-Aug-2020	linjiawei <[email protected]>	Merge master into temp-lsu-test cputest.sh /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
63163217	06-Aug-2020	linjiawei <[email protected]>	debug: add a cputest script /XiangShan/Makefile /XiangShan/build.sc cputest.sh /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
2b2ffe78	05-Aug-2020	William Wang <[email protected]>	Merge branch 'temp-lsu-test' of https://github.com/RISCVERS/XiangShan into temp-lsu-test /XiangShan/Makefile /XiangShan/build.sc Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
f888cfd5	05-Aug-2020	William Wang <[email protected]>	chore: fix cputest in debug/Makefile Makefile /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
8a1d27c4	04-Aug-2020	LinJiawei <[email protected]>	Merge master into temp-lsu-test /XiangShan/Makefile /XiangShan/build.sc Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
1854804d	30-Jul-2020	zhanglinjuan <[email protected]>	Merge branch 'dev-ifu-predecode' into dev-frontend-ifu Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala
fd14e3c8	28-Jul-2020	zhanglinjuan <[email protected]>	Merge branch 'master' into dev-bpu-rvc /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/scala/IFUtest/PDtest.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
6e3ea132	26-Jul-2020	LinJiawei <[email protected]>	Merge master into temp-lsu-test; turn off Lsroq /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
4e4bcef1	24-Jul-2020	jinyue110 <[email protected]>	BTB: add couter Reg instead of using SRAM Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/test/csrc/monitor.cpp
b96c44c9	23-Jul-2020	LinJiawei <[email protected]>	Unit-test: update code /XiangShan/Makefile Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
77de6f52	22-Jul-2020	zhanglinjuan <[email protected]>	frontend/multiplier: fix pipeline bugs and mul flush logic 1. bpu: fix instrValid in stage3 2. multiplier: flush validVec according to the previous flushVec /XiangShan/Makefile Makefile /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
714bcf44	20-Jul-2020	GouLingrui <[email protected]>	Merge remote-tracking branch 'origin/move-bpu-perfcnt' into dev-bpu-rebase-tage 1 /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala
500cbc10	20-Jul-2020	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-lsu-test Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala
ae7c6ced	20-Jul-2020	William Wang <[email protected]>	Makefile: update debug/Makefile /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile Makefile /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZicsr.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/IFUtest/IFUtest.scala /XiangShan/src/test/scala/top/XSSim.scala
398001c4	19-Jul-2020	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into temp-lsu-test /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/build.sbt Makefile /XiangShan/src/main/scala/bus/simplebus/SimpleBus.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZicsr.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/IFUtest/IFUtest.scala /XiangShan/src/test/scala/top/XSSim.scala
daa9644c	15-Jul-2020	GouLingrui <[email protected]>	BPU: fix log in JBTAC Makefile /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala
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