xref: /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala (revision 2b2ffe78345f1b87af9bfe5be5ced3a3debe0b9a) 
1package xiangshan.backend.rename
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils.XSInfo
7
8class Rename extends XSModule {
9  val io = IO(new Bundle() {
10    val redirect = Flipped(ValidIO(new Redirect))
11    val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
12    val wbIntResults = Vec(NRIntWritePorts, Flipped(ValidIO(new ExuOutput)))
13    val wbFpResults = Vec(NRFpWritePorts, Flipped(ValidIO(new ExuOutput)))
14    val intRfReadAddr = Vec(NRIntReadPorts + NRMemReadPorts, Input(UInt(PhyRegIdxWidth.W)))
15    val fpRfReadAddr = Vec(NRFpReadPorts, Input(UInt(PhyRegIdxWidth.W)))
16    val intPregRdy = Vec(NRIntReadPorts + NRMemReadPorts, Output(Bool()))
17    val fpPregRdy = Vec(NRFpReadPorts, Output(Bool()))
18    // from decode buffer
19    val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
20    // to dispatch1
21    val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
22  })
23
24  def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = {
25    XSInfo(
26      in.valid && in.ready,
27      p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " +
28        p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " +
29        p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " +
30        p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " +
31        p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " +
32        p"old_pdest:${out.bits.old_pdest} " +
33        p"out v:${out.valid} r:${out.ready}\n"
34    )
35  }
36
37  for((x,y) <- io.in.zip(io.out)){
38    printRenameInfo(x, y)
39  }
40
41  val fpFreeList, intFreeList = Module(new FreeList).io
42  val fpRat = Module(new RenameTable(float = true)).io
43  val intRat = Module(new RenameTable(float = false)).io
44  val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)).io
45  val intBusyTable = Module(new BusyTable(NRIntReadPorts+NRMemReadPorts, NRIntWritePorts)).io
46
47  fpFreeList.redirect := io.redirect
48  intFreeList.redirect := io.redirect
49
50  val flush = io.redirect.valid && io.redirect.bits.isException
51  fpRat.flush := flush
52  intRat.flush := flush
53  fpBusyTable.flush := flush
54  intBusyTable.flush := flush
55
56  def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
57    {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
58  }
59
60  val uops = Wire(Vec(RenameWidth, new MicroOp))
61
62  uops.foreach( uop => {
63//    uop.brMask := DontCare
64//    uop.brTag := DontCare
65    uop.src1State := DontCare
66    uop.src2State := DontCare
67    uop.src3State := DontCare
68    uop.roqIdx := DontCare
69    uop.moqIdx := DontCare
70  })
71
72  var lastReady = WireInit(io.out(0).ready)
73  // debug assert
74  val outRdy = Cat(io.out.map(_.ready))
75  assert(outRdy===0.U || outRdy.andR())
76  for(i <- 0 until RenameWidth) {
77    uops(i).cf := io.in(i).bits.cf
78    uops(i).ctrl := io.in(i).bits.ctrl
79    uops(i).brTag := io.in(i).bits.brTag
80
81    val inValid = io.in(i).valid
82
83    // alloc a new phy reg
84    val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits)
85    val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits)
86    fpFreeList.allocReqs(i) := needFpDest && lastReady
87    intFreeList.allocReqs(i) := needIntDest && lastReady
88    val fpCanAlloc = fpFreeList.canAlloc(i)
89    val intCanAlloc = intFreeList.canAlloc(i)
90    val this_can_alloc = Mux(
91      needIntDest,
92      intCanAlloc,
93      Mux(
94        needFpDest,
95        fpCanAlloc,
96        true.B
97      )
98    )
99    io.in(i).ready := lastReady && this_can_alloc
100
101    // do checkpoints when a branch inst come
102    for(fl <- Seq(fpFreeList, intFreeList)){
103      fl.cpReqs(i).valid := inValid
104      fl.cpReqs(i).bits := io.in(i).bits.brTag
105    }
106
107    lastReady = io.in(i).ready
108
109    uops(i).pdest := Mux(needIntDest,
110      intFreeList.pdests(i),
111      Mux(
112        uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen,
113        0.U, fpFreeList.pdests(i)
114      )
115    )
116
117    io.out(i).valid := io.in(i).fire()
118    io.out(i).bits := uops(i)
119
120    // write rename table
121    def writeRat(fp: Boolean) = {
122      val rat = if(fp) fpRat else intRat
123      val freeList = if(fp) fpFreeList else intFreeList
124      val busyTable = if(fp) fpBusyTable else intBusyTable
125      // speculative inst write
126      val specWen = freeList.allocReqs(i) && freeList.canAlloc(i)
127      // walk back write
128      val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop)
129      val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk
130
131      rat.specWritePorts(i).wen := specWen || walkWen
132      rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest)
133      rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest)
134
135      XSInfo(walkWen,
136        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" +
137          p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
138      )
139
140      rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk
141      rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest
142      rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest
143
144      XSInfo(rat.archWritePorts(i).wen,
145        {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
146          p" pdest:${rat.archWritePorts(i).wdata}\n"
147      )
148
149      freeList.deallocReqs(i) := rat.archWritePorts(i).wen
150      freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest
151
152      // set phy reg status to busy
153      busyTable.allocPregs(i).valid := specWen
154      busyTable.allocPregs(i).bits := freeList.pdests(i)
155    }
156
157    writeRat(fp = false)
158    writeRat(fp = true)
159
160    // read rename table
161    def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = {
162      val rat = if(fp) fpRat else intRat
163      val srcCnt = lsrcList.size
164      val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W)))
165      val old_pdest = Wire(UInt(PhyRegIdxWidth.W))
166      for(k <- 0 until srcCnt+1){
167        val rportIdx = i * (srcCnt+1) + k
168        if(k != srcCnt){
169          rat.readPorts(rportIdx).addr := lsrcList(k)
170          psrcVec(k) := rat.readPorts(rportIdx).rdata
171        } else {
172          rat.readPorts(rportIdx).addr := ldest
173          old_pdest := rat.readPorts(rportIdx).rdata
174        }
175      }
176      (psrcVec, old_pdest)
177    }
178    val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3)
179    val ldest = uops(i).ctrl.ldest
180    val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false)
181    val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true)
182    uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0))
183    uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1))
184    uops(i).psrc3 := fpPhySrcVec(2)
185    uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest)
186  }
187
188
189  def updateBusyTable(fp: Boolean) = {
190    val wbResults = if(fp) io.wbFpResults else io.wbIntResults
191    val busyTable = if(fp) fpBusyTable else intBusyTable
192    for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){
193      setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop)
194      setPhyRegRdy.bits := wb.bits.uop.pdest
195    }
196  }
197
198  updateBusyTable(false)
199  updateBusyTable(true)
200
201  intBusyTable.rfReadAddr <> io.intRfReadAddr
202  intBusyTable.pregRdy <> io.intPregRdy
203  fpBusyTable.rfReadAddr <> io.fpRfReadAddr
204  fpBusyTable.pregRdy <> io.fpPregRdy
205}
206