1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import xiangshan.mem._ 13import xiangshan.cache.{DCacheParameters, ICacheParameters} 14import bus.tilelink.{TLArbiter, TLCached, TLMasterUtilities, TLParameters} 15import utils._ 16 17case class XSCoreParameters 18( 19 XLEN: Int = 64, 20 HasMExtension: Boolean = true, 21 HasCExtension: Boolean = true, 22 HasDiv: Boolean = true, 23 HasICache: Boolean = true, 24 HasDCache: Boolean = true, 25 EnableStoreQueue: Boolean = true, 26 AddrBits: Int = 64, 27 VAddrBits: Int = 39, 28 PAddrBits: Int = 32, 29 HasFPU: Boolean = true, 30 FectchWidth: Int = 8, 31 EnableBPU: Boolean = true, 32 EnableBPD: Boolean = true, 33 EnableRAS: Boolean = false, 34 EnableLB: Boolean = false, 35 HistoryLength: Int = 64, 36 BtbSize: Int = 256, 37 JbtacSize: Int = 1024, 38 JbtacBanks: Int = 8, 39 RasSize: Int = 16, 40 CacheLineSize: Int = 512, 41 UBtbWays: Int = 16, 42 BtbWays: Int = 2, 43 IBufSize: Int = 64, 44 DecodeWidth: Int = 6, 45 RenameWidth: Int = 6, 46 CommitWidth: Int = 6, 47 BrqSize: Int = 16, 48 IssQueSize: Int = 8, 49 NRPhyRegs: Int = 128, 50 NRIntReadPorts: Int = 8, 51 NRIntWritePorts: Int = 8, 52 NRFpReadPorts: Int = 14, 53 NRFpWritePorts: Int = 8, 54 LsroqSize: Int = 16, 55 RoqSize: Int = 32, 56 dpParams: DispatchParameters = DispatchParameters( 57 DqEnqWidth = 4, 58 IntDqSize = 64, 59 FpDqSize = 64, 60 LsDqSize = 64, 61 IntDqDeqWidth = 4, 62 FpDqDeqWidth = 4, 63 LsDqDeqWidth = 4, 64 IntDqReplayWidth = 4, 65 FpDqReplayWidth = 4, 66 LsDqReplayWidth = 4 67 ), 68 exuParameters: ExuParameters = ExuParameters( 69 JmpCnt = 1, 70 AluCnt = 4, 71 MulCnt = 0, 72 MduCnt = 2, 73 FmacCnt = 0, 74 FmiscCnt = 0, 75 FmiscDivSqrtCnt = 0, 76 LduCnt = 2, 77 StuCnt = 2 78 ), 79 LoadPipelineWidth: Int = 2, 80 StorePipelineWidth: Int = 2, 81 StoreBufferSize: Int = 16, 82 RefillSize: Int = 512 83) 84 85trait HasXSParameter { 86 87 val core = Parameters.get.coreParameters 88 val env = Parameters.get.envParameters 89 90 val XLEN = core.XLEN 91 val HasMExtension = core.HasMExtension 92 val HasCExtension = core.HasCExtension 93 val HasDiv = core.HasDiv 94 val HasIcache = core.HasICache 95 val HasDcache = core.HasDCache 96 val EnableStoreQueue = core.EnableStoreQueue 97 val AddrBits = core.AddrBits // AddrBits is used in some cases 98 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 99 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 100 val AddrBytes = AddrBits / 8 // unused 101 val DataBits = XLEN 102 val DataBytes = DataBits / 8 103 val HasFPU = core.HasFPU 104 val FetchWidth = core.FectchWidth 105 val PredictWidth = FetchWidth * 2 106 val EnableBPU = core.EnableBPU 107 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 108 val EnableRAS = core.EnableRAS 109 val EnableLB = core.EnableLB 110 val HistoryLength = core.HistoryLength 111 val BtbSize = core.BtbSize 112 // val BtbWays = 4 113 val BtbBanks = PredictWidth 114 // val BtbSets = BtbSize / BtbWays 115 val JbtacSize = core.JbtacSize 116 val JbtacBanks = core.JbtacBanks 117 val RasSize = core.RasSize 118 val CacheLineSize = core.CacheLineSize 119 val CacheLineHalfWord = CacheLineSize / 16 120 val ExtHistoryLength = HistoryLength * 2 121 val UBtbWays = core.UBtbWays 122 val BtbWays = core.BtbWays 123 val IBufSize = core.IBufSize 124 val DecodeWidth = core.DecodeWidth 125 val RenameWidth = core.RenameWidth 126 val CommitWidth = core.CommitWidth 127 val BrqSize = core.BrqSize 128 val IssQueSize = core.IssQueSize 129 val BrTagWidth = log2Up(BrqSize) 130 val NRPhyRegs = core.NRPhyRegs 131 val PhyRegIdxWidth = log2Up(NRPhyRegs) 132 val LsroqSize = core.LsroqSize // 64 133 val RoqSize = core.RoqSize 134 val InnerRoqIdxWidth = log2Up(RoqSize) 135 val RoqIdxWidth = InnerRoqIdxWidth + 1 136 val InnerLsroqIdxWidth = log2Up(LsroqSize) 137 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 138 val dpParams = core.dpParams 139 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 140 val exuParameters = core.exuParameters 141 val NRIntReadPorts = core.NRIntReadPorts 142 val NRIntWritePorts = core.NRIntWritePorts 143 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 144 val NRFpReadPorts = core.NRFpReadPorts 145 val NRFpWritePorts = core.NRFpWritePorts 146 val LoadPipelineWidth = core.LoadPipelineWidth 147 val StorePipelineWidth = core.StorePipelineWidth 148 val StoreBufferSize = core.StoreBufferSize 149 val RefillSize = core.RefillSize 150 151 val l1BusDataWidth = 64 152 val l1BusParams = TLParameters( 153 addressBits = PAddrBits, 154 dataBits = l1BusDataWidth, 155 sourceBits = 3, 156 sinkBits = 3 157 ) 158 159 val icacheParameters = ICacheParameters( 160 ) 161 162 val LRSCCycles = 16 163 val dcacheParameters = DCacheParameters( 164 tagECC = Some("secded"), 165 dataECC = Some("secded"), 166 busParams = l1BusParams 167 ) 168} 169 170trait HasXSLog { this: Module => 171 implicit val moduleName: String = this.name 172} 173 174abstract class XSModule extends Module 175 with HasXSParameter 176 with HasExceptionNO 177 with HasXSLog 178 179//remove this trait after impl module logic 180trait NeedImpl { this: Module => 181 override protected def IO[T <: Data](iodef: T): T = { 182 val io = chisel3.experimental.IO(iodef) 183 io <> DontCare 184 io 185 } 186} 187 188abstract class XSBundle extends Bundle 189 with HasXSParameter 190 191case class EnviromentParameters 192( 193 FPGAPlatform: Boolean = true, 194 EnableDebug: Boolean = false 195) 196 197object AddressSpace extends HasXSParameter { 198 // (start, size) 199 // address out of MMIO will be considered as DRAM 200 def mmio = List( 201 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 202 (0x40000000L, 0x40000000L) // external devices 203 ) 204 205 def isMMIO(addr: UInt): Bool = mmio.map(range => { 206 require(isPow2(range._2)) 207 val bits = log2Up(range._2) 208 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 209 }).reduce(_ || _) 210} 211 212 213class TLReqProducer extends XSModule { 214 val io = IO(new TLCached(l1BusParams)) 215 216 io <> DontCare 217 218 val addr = RegInit("h80000000".U) 219 addr := addr + 4.U 220 val (legal, bundle) = TLMasterUtilities.Get(io.params, 0.U, addr, 3.U) 221 io.a.bits := bundle 222 io.a.valid := true.B 223 assert(legal) 224 io.d.ready := true.B 225 when(io.a.fire()){ 226 io.a.bits.dump() 227 } 228 when(io.d.fire()){ 229 io.d.bits.dump() 230 } 231} 232 233class XSCore extends XSModule { 234 val io = IO(new Bundle { 235 val mem = new TLCached(l1BusParams) 236 val mmio = new TLCached(l1BusParams) 237 }) 238 239 // val fakecache = Module(new TLReqProducer) 240 // io.mem <> fakecache.io 241 242 io.mmio <> DontCare 243 244 val front = Module(new Frontend) 245 val backend = Module(new Backend) 246 val mem = Module(new Memend) 247 248 front.io.backend <> backend.io.frontend 249 mem.io.backend <> backend.io.mem 250 mem.io.mem <> io.mem 251 mem.io.mmio <> io.mmio 252 253 backend.io.memMMU.imem <> DontCare 254 backend.io.memMMU.dmem <> DontCare 255 256} 257