| Makefile (8c9adf0c855c8b89abcd2e3d8755876e2c2ee4cd) | Makefile (414f1bf40efa355d251b0dc2e7f2060a7eaf03b7) |
|---|---|
| 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 52 unchanged lines hidden (view full) --- 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" | 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 52 unchanged lines hidden (view full) --- 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" |
| 69RELEASE_ARGS += $(MFC_ARGS) 70DEBUG_ARGS += $(MFC_ARGS) 71PLDM_ARGS += $(MFC_ARGS) | |
| 72 | 69 |
| 70# prefix of XSTop or XSNoCTop |
|
| 73ifneq ($(XSTOP_PREFIX),) | 71ifneq ($(XSTOP_PREFIX),) |
| 74RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 75DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 76PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) | 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) |
| 77endif 78 | 73endif 74 |
| 75# IMSIC use TileLink rather than AXI4Lite |
|
| 79ifeq ($(IMSIC_USE_TL),1) | 76ifeq ($(IMSIC_USE_TL),1) |
| 80RELEASE_ARGS += --imsic-use-tl 81DEBUG_ARGS += --imsic-use-tl 82PLDM_ARGS += --imsic-use-tl | 77COMMON_EXTRA_ARGS += --imsic-use-tl |
| 83endif 84 | 78endif 79 |
| 80# L2 cache size in KB 81ifneq ($(L2_CACHE_SIZE),) 82COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 83endif 84 85# L3 cache size in KB 86ifneq ($(L3_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 88endif 89 90# public args sumup 91RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 92DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 93PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 94 |
|
| 85# co-simulation with DRAMsim3 86ifeq ($(WITH_DRAMSIM3),1) 87ifndef DRAMSIM3_HOME 88$(error DRAMSIM3_HOME is not set) 89endif 90override SIM_ARGS += --with-dramsim3 91endif 92 --- 166 unchanged lines hidden --- | 95# co-simulation with DRAMsim3 96ifeq ($(WITH_DRAMSIM3),1) 97ifndef DRAMSIM3_HOME 98$(error DRAMSIM3_HOME is not set) 99endif 100override SIM_ARGS += --with-dramsim3 101endif 102 --- 166 unchanged lines hidden --- |