1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# L2 cache size in KB 81ifneq ($(L2_CACHE_SIZE),) 82COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 83endif 84 85# L3 cache size in KB 86ifneq ($(L3_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 88endif 89 90# public args sumup 91RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 92DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 93PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 94 95# co-simulation with DRAMsim3 96ifeq ($(WITH_DRAMSIM3),1) 97ifndef DRAMSIM3_HOME 98$(error DRAMSIM3_HOME is not set) 99endif 100override SIM_ARGS += --with-dramsim3 101endif 102 103# run emu with chisel-db 104ifeq ($(WITH_CHISELDB),1) 105override SIM_ARGS += --with-chiseldb 106endif 107 108# run emu with chisel-db 109ifeq ($(WITH_ROLLINGDB),1) 110override SIM_ARGS += --with-rollingdb 111endif 112 113# enable ResetGen 114ifeq ($(WITH_RESETGEN),1) 115override SIM_ARGS += --reset-gen 116endif 117 118# run with disable all perf 119ifeq ($(DISABLE_PERF),1) 120override SIM_ARGS += --disable-perf 121endif 122 123# run with disable all db 124ifeq ($(DISABLE_ALWAYSDB),1) 125override SIM_ARGS += --disable-alwaysdb 126endif 127 128# dynamic switch CONSTANTIN 129ifeq ($(WITH_CONSTANTIN),1) 130override SIM_ARGS += --with-constantin 131endif 132 133# emu for the release version 134RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 135DEBUG_ARGS += --enable-difftest 136PLDM_ARGS += --fpga-platform --enable-difftest 137ifeq ($(RELEASE),1) 138override SIM_ARGS += $(RELEASE_ARGS) 139else ifeq ($(PLDM),1) 140override SIM_ARGS += $(PLDM_ARGS) 141else 142override SIM_ARGS += $(DEBUG_ARGS) 143endif 144 145TIMELOG = $(BUILD_DIR)/time.log 146TIME_CMD = time -avp -o $(TIMELOG) 147 148ifeq ($(PLDM),1) 149SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 150SED_ENDIF = `endif // not def SYNTHESIS 151endif 152 153.DEFAULT_GOAL = verilog 154 155help: 156 mill -i xiangshan.runMain $(FPGATOP) --help 157 158version: 159 mill -i xiangshan.runMain $(FPGATOP) --version 160 161jar: 162 mill -i xiangshan.assembly 163 164test-jar: 165 mill -i xiangshan.test.assembly 166 167$(TOP_V): $(SCALA_FILE) 168 mkdir -p $(@D) 169 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 170 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 171 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 172ifeq ($(CHISEL_TARGET),systemverilog) 173 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 174 @git log -n 1 >> .__head__ 175 @git diff >> .__diff__ 176 @sed -i 's/^/\/\// ' .__head__ 177 @sed -i 's/^/\/\//' .__diff__ 178 @cat .__head__ .__diff__ $@ > .__out__ 179 @mv .__out__ $@ 180 @rm .__head__ .__diff__ 181endif 182 183verilog: $(TOP_V) 184 185$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 186 mkdir -p $(@D) 187 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 188 @date -R | tee -a $(TIMELOG) 189 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 190 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 191 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 192ifeq ($(CHISEL_TARGET),systemverilog) 193 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 194 @git log -n 1 >> .__head__ 195 @git diff >> .__diff__ 196 @sed -i 's/^/\/\// ' .__head__ 197 @sed -i 's/^/\/\//' .__diff__ 198 @cat .__head__ .__diff__ $@ > .__out__ 199 @mv .__out__ $@ 200 @rm .__head__ .__diff__ 201ifeq ($(PLDM),1) 202 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 203 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 204else 205ifeq ($(ENABLE_XPROP),1) 206 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 207else 208 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 209endif 210endif 211 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 212endif 213 214sim-verilog: $(SIM_TOP_V) 215 216clean: 217 $(MAKE) -C ./difftest clean 218 rm -rf $(BUILD_DIR) 219 220init: 221 git submodule update --init 222 cd rocket-chip && git submodule update --init cde hardfloat 223 cd openLLC && git submodule update --init openNCB 224 225bump: 226 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 227 228bsp: 229 mill -i mill.bsp.BSP/install 230 231idea: 232 mill -i mill.idea.GenIdea/idea 233 234check-format: 235 mill xiangshan.checkFormat 236 237reformat: 238 mill xiangshan.reformat 239 240# verilator simulation 241emu: sim-verilog 242 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 243 244emu-run: emu 245 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 246 247# vcs simulation 248simv: sim-verilog 249 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 250 251simv-run: 252 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 253 254# palladium simulation 255pldm-build: sim-verilog 256 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 257 258pldm-run: 259 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 260 261pldm-debug: 262 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 263 264include Makefile.test 265 266include src/main/scala/device/standalone/standalone_device.mk 267 268.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 269