1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69RELEASE_ARGS += $(MFC_ARGS) 70DEBUG_ARGS += $(MFC_ARGS) 71PLDM_ARGS += $(MFC_ARGS) 72 73ifneq ($(XSTOP_PREFIX),) 74RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 75DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 76PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 77endif 78 79ifeq ($(IMSIC_USE_TL),1) 80RELEASE_ARGS += --imsic-use-tl 81DEBUG_ARGS += --imsic-use-tl 82PLDM_ARGS += --imsic-use-tl 83endif 84 85# co-simulation with DRAMsim3 86ifeq ($(WITH_DRAMSIM3),1) 87ifndef DRAMSIM3_HOME 88$(error DRAMSIM3_HOME is not set) 89endif 90override SIM_ARGS += --with-dramsim3 91endif 92 93# run emu with chisel-db 94ifeq ($(WITH_CHISELDB),1) 95override SIM_ARGS += --with-chiseldb 96endif 97 98# run emu with chisel-db 99ifeq ($(WITH_ROLLINGDB),1) 100override SIM_ARGS += --with-rollingdb 101endif 102 103# enable ResetGen 104ifeq ($(WITH_RESETGEN),1) 105override SIM_ARGS += --reset-gen 106endif 107 108# run with disable all perf 109ifeq ($(DISABLE_PERF),1) 110override SIM_ARGS += --disable-perf 111endif 112 113# run with disable all db 114ifeq ($(DISABLE_ALWAYSDB),1) 115override SIM_ARGS += --disable-alwaysdb 116endif 117 118# dynamic switch CONSTANTIN 119ifeq ($(WITH_CONSTANTIN),1) 120override SIM_ARGS += --with-constantin 121endif 122 123# emu for the release version 124RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 125DEBUG_ARGS += --enable-difftest 126PLDM_ARGS += --fpga-platform --enable-difftest 127ifeq ($(RELEASE),1) 128override SIM_ARGS += $(RELEASE_ARGS) 129else ifeq ($(PLDM),1) 130override SIM_ARGS += $(PLDM_ARGS) 131else 132override SIM_ARGS += $(DEBUG_ARGS) 133endif 134 135TIMELOG = $(BUILD_DIR)/time.log 136TIME_CMD = time -avp -o $(TIMELOG) 137 138ifeq ($(PLDM),1) 139SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 140SED_ENDIF = `endif // not def SYNTHESIS 141endif 142 143.DEFAULT_GOAL = verilog 144 145help: 146 mill -i xiangshan.runMain $(FPGATOP) --help 147 148version: 149 mill -i xiangshan.runMain $(FPGATOP) --version 150 151jar: 152 mill -i xiangshan.assembly 153 154test-jar: 155 mill -i xiangshan.test.assembly 156 157$(TOP_V): $(SCALA_FILE) 158 mkdir -p $(@D) 159 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 160 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 161 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 162ifeq ($(CHISEL_TARGET),systemverilog) 163 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 164 @git log -n 1 >> .__head__ 165 @git diff >> .__diff__ 166 @sed -i 's/^/\/\// ' .__head__ 167 @sed -i 's/^/\/\//' .__diff__ 168 @cat .__head__ .__diff__ $@ > .__out__ 169 @mv .__out__ $@ 170 @rm .__head__ .__diff__ 171endif 172 173verilog: $(TOP_V) 174 175$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 176 mkdir -p $(@D) 177 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 178 @date -R | tee -a $(TIMELOG) 179 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 180 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 181 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 182ifeq ($(CHISEL_TARGET),systemverilog) 183 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 184 @git log -n 1 >> .__head__ 185 @git diff >> .__diff__ 186 @sed -i 's/^/\/\// ' .__head__ 187 @sed -i 's/^/\/\//' .__diff__ 188 @cat .__head__ .__diff__ $@ > .__out__ 189 @mv .__out__ $@ 190 @rm .__head__ .__diff__ 191ifeq ($(PLDM),1) 192 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 193 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 194else 195ifeq ($(ENABLE_XPROP),1) 196 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 197else 198 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 199endif 200endif 201 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 202endif 203 204sim-verilog: $(SIM_TOP_V) 205 206clean: 207 $(MAKE) -C ./difftest clean 208 rm -rf $(BUILD_DIR) 209 210init: 211 git submodule update --init 212 cd rocket-chip && git submodule update --init cde hardfloat 213 cd openLLC && git submodule update --init openNCB 214 215bump: 216 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 217 218bsp: 219 mill -i mill.bsp.BSP/install 220 221idea: 222 mill -i mill.idea.GenIdea/idea 223 224check-format: 225 mill xiangshan.checkFormat 226 227reformat: 228 mill xiangshan.reformat 229 230# verilator simulation 231emu: sim-verilog 232 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 233 234emu-run: emu 235 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 236 237# vcs simulation 238simv: sim-verilog 239 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 240 241simv-run: 242 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 243 244# palladium simulation 245pldm-build: sim-verilog 246 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 247 248pldm-run: 249 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 250 251pldm-debug: 252 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 253 254include Makefile.test 255 256include src/main/scala/device/standalone/standalone_device.mk 257 258.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 259