| Makefile (4a699e275a42daaf03e4f014bad0bb16d893e6ff) | Makefile (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345) |
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| 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 63 unchanged lines hidden (view full) --- 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 | 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 63 unchanged lines hidden (view full) --- 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 |
| 80# IMSIC use TileLink rather than AXI4Lite 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --enable-dfx 83endif 84 |
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| 80# L2 cache size in KB 81ifneq ($(L2_CACHE_SIZE),) 82COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 83endif 84 85# L3 cache size in KB 86ifneq ($(L3_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) --- 88 unchanged lines hidden (view full) --- 176 mill -i xiangshan.runMain $(FPGATOP) --version 177 178jar: 179 mill -i xiangshan.assembly 180 181test-jar: 182 mill -i xiangshan.test.assembly 183 | 85# L2 cache size in KB 86ifneq ($(L2_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 88endif 89 90# L3 cache size in KB 91ifneq ($(L3_CACHE_SIZE),) 92COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) --- 88 unchanged lines hidden (view full) --- 181 mill -i xiangshan.runMain $(FPGATOP) --version 182 183jar: 184 mill -i xiangshan.assembly 185 186test-jar: 187 mill -i xiangshan.test.assembly 188 |
| 189comp: 190 mill -i xiangshan.compile 191 mill -i xiangshan.test.compile 192 |
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| 184$(TOP_V): $(SCALA_FILE) 185 mkdir -p $(@D) 186 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 187 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 188 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 189ifeq ($(CHISEL_TARGET),systemverilog) 190 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 191 @git log -n 1 >> .__head__ --- 94 unchanged lines hidden --- | 193$(TOP_V): $(SCALA_FILE) 194 mkdir -p $(@D) 195 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 196 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 197 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 198ifeq ($(CHISEL_TARGET),systemverilog) 199 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 200 @git log -n 1 >> .__head__ --- 94 unchanged lines hidden --- |