xref: /nrf52832-nimble/rt-thread/components/lwp/arch/arm/cortex-a9/lwp_gcc.S (revision 104654410c56c573564690304ae786df310c91fc)
1/*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2018-12-10     Jesven       first version
9 */
10
11#define  Mode_USR       0x10
12#define  Mode_FIQ       0x11
13#define  Mode_IRQ       0x12
14#define  Mode_SVC       0x13
15#define  Mode_MON       0x16
16#define  Mode_ABT       0x17
17#define  Mode_UDF       0x1B
18#define  Mode_SYS       0x1F
19
20#define A_Bit        0x100
21#define I_Bit        0x80 @; when I bit is set, IRQ is disabled
22#define F_Bit        0x40 @; when F bit is set, FIQ is disabled
23#define T_Bit        0x20
24
25.cpu cortex-a9
26.syntax unified
27.text
28
29/*
30 * void lwp_user_entry(args, text, data);
31 */
32.global lwp_user_entry
33.type lwp_user_entry, % function
34lwp_user_entry:
35    mrs     r9, cpsr
36    bic     r9, #0x1f
37    orr     r9, #Mode_USR
38    cpsid i
39    msr     spsr, r9
40
41    /* set data address. */
42    mov     r9, r2
43    movs    pc, r1
44
45/*
46 * void SVC_Handler(void);
47 */
48.global SVC_Handler
49.type SVC_Handler, % function
50SVC_Handler:
51    push {lr}
52    mrs lr, spsr
53    push {r4, r5, lr}
54    cpsie i
55
56    push {r0 - r3, r12}
57    and r0, r7, #0xff
58    bl lwp_get_sys_api
59    cmp r0, #0           /* r0 = api */
60    mov lr, r0
61    pop {r0 - r3, r12}
62    beq svc_exit
63    blx lr
64
65svc_exit:
66    cpsid i
67    pop {r4, r5, lr}
68    msr spsr_cxsf, lr
69    pop {lr}
70    movs pc, lr
71