1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 /* AD7124 input sources */
99 #define AD7124_INPUT_TEMPSENSOR 16
100 #define AD7124_INPUT_AVSS 17
101
102 enum ad7124_ids {
103 ID_AD7124_4,
104 ID_AD7124_8,
105 };
106
107 enum ad7124_ref_sel {
108 AD7124_REFIN1,
109 AD7124_REFIN2,
110 AD7124_INT_REF,
111 AD7124_AVDD_REF,
112 };
113
114 enum ad7124_power_mode {
115 AD7124_LOW_POWER,
116 AD7124_MID_POWER,
117 AD7124_FULL_POWER,
118 };
119
120 static const unsigned int ad7124_gain[8] = {
121 1, 2, 4, 8, 16, 32, 64, 128
122 };
123
124 static const unsigned int ad7124_reg_size[] = {
125 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
126 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
127 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
128 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
129 3, 3, 3, 3, 3
130 };
131
132 static const int ad7124_master_clk_freq_hz[3] = {
133 [AD7124_LOW_POWER] = 76800,
134 [AD7124_MID_POWER] = 153600,
135 [AD7124_FULL_POWER] = 614400,
136 };
137
138 static const char * const ad7124_ref_names[] = {
139 [AD7124_REFIN1] = "refin1",
140 [AD7124_REFIN2] = "refin2",
141 [AD7124_INT_REF] = "int",
142 [AD7124_AVDD_REF] = "avdd",
143 };
144
145 struct ad7124_chip_info {
146 const char *name;
147 unsigned int chip_id;
148 unsigned int num_inputs;
149 };
150
151 struct ad7124_channel_config {
152 bool live;
153 unsigned int cfg_slot;
154 /*
155 * Following fields are used to compare for equality. If you
156 * make adaptations in it, you most likely also have to adapt
157 * ad7124_find_similar_live_cfg(), too.
158 */
159 struct_group(config_props,
160 enum ad7124_ref_sel refsel;
161 bool bipolar;
162 bool buf_positive;
163 bool buf_negative;
164 unsigned int vref_mv;
165 unsigned int pga_bits;
166 unsigned int odr;
167 unsigned int odr_sel_bits;
168 unsigned int filter_type;
169 );
170 };
171
172 struct ad7124_channel {
173 unsigned int nr;
174 struct ad7124_channel_config cfg;
175 unsigned int ain;
176 unsigned int slot;
177 };
178
179 struct ad7124_state {
180 const struct ad7124_chip_info *chip_info;
181 struct ad_sigma_delta sd;
182 struct ad7124_channel *channels;
183 struct regulator *vref[4];
184 struct clk *mclk;
185 unsigned int adc_control;
186 unsigned int num_channels;
187 struct mutex cfgs_lock; /* lock for configs access */
188 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
189 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
190 };
191
192 static const struct iio_chan_spec ad7124_channel_template = {
193 .type = IIO_VOLTAGE,
194 .indexed = 1,
195 .differential = 1,
196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
197 BIT(IIO_CHAN_INFO_SCALE) |
198 BIT(IIO_CHAN_INFO_OFFSET) |
199 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
200 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
201 .scan_type = {
202 .sign = 'u',
203 .realbits = 24,
204 .storagebits = 32,
205 .endianness = IIO_BE,
206 },
207 };
208
209 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
210 [ID_AD7124_4] = {
211 .name = "ad7124-4",
212 .chip_id = CHIPID_AD7124_4,
213 .num_inputs = 8,
214 },
215 [ID_AD7124_8] = {
216 .name = "ad7124-8",
217 .chip_id = CHIPID_AD7124_8,
218 .num_inputs = 16,
219 },
220 };
221
ad7124_find_closest_match(const int * array,unsigned int size,int val)222 static int ad7124_find_closest_match(const int *array,
223 unsigned int size, int val)
224 {
225 int i, idx;
226 unsigned int diff_new, diff_old;
227
228 diff_old = U32_MAX;
229 idx = 0;
230
231 for (i = 0; i < size; i++) {
232 diff_new = abs(val - array[i]);
233 if (diff_new < diff_old) {
234 diff_old = diff_new;
235 idx = i;
236 }
237 }
238
239 return idx;
240 }
241
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)242 static int ad7124_spi_write_mask(struct ad7124_state *st,
243 unsigned int addr,
244 unsigned long mask,
245 unsigned int val,
246 unsigned int bytes)
247 {
248 unsigned int readval;
249 int ret;
250
251 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
252 if (ret < 0)
253 return ret;
254
255 readval &= ~mask;
256 readval |= val;
257
258 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
259 }
260
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)261 static int ad7124_set_mode(struct ad_sigma_delta *sd,
262 enum ad_sigma_delta_mode mode)
263 {
264 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
265
266 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
267 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
268
269 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
270 }
271
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)272 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
273 {
274 unsigned int fclk, odr_sel_bits;
275
276 fclk = clk_get_rate(st->mclk);
277 /*
278 * FS[10:0] = fCLK / (fADC x 32) where:
279 * fADC is the output data rate
280 * fCLK is the master clock frequency
281 * FS[10:0] are the bits in the filter register
282 * FS[10:0] can have a value from 1 to 2047
283 */
284 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
285 if (odr_sel_bits < 1)
286 odr_sel_bits = 1;
287 else if (odr_sel_bits > 2047)
288 odr_sel_bits = 2047;
289
290 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
291 st->channels[channel].cfg.live = false;
292
293 /* fADC = fCLK / (FS[10:0] x 32) */
294 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
295 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
296 }
297
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)298 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
299 unsigned int channel)
300 {
301 unsigned int fadc;
302
303 fadc = st->channels[channel].cfg.odr;
304
305 switch (st->channels[channel].cfg.filter_type) {
306 case AD7124_SINC3_FILTER:
307 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
308 case AD7124_SINC4_FILTER:
309 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
310 default:
311 return -EINVAL;
312 }
313 }
314
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)315 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
316 unsigned int freq)
317 {
318 unsigned int sinc4_3db_odr;
319 unsigned int sinc3_3db_odr;
320 unsigned int new_filter;
321 unsigned int new_odr;
322
323 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
324 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
325
326 if (sinc4_3db_odr > sinc3_3db_odr) {
327 new_filter = AD7124_SINC3_FILTER;
328 new_odr = sinc4_3db_odr;
329 } else {
330 new_filter = AD7124_SINC4_FILTER;
331 new_odr = sinc3_3db_odr;
332 }
333
334 if (new_odr != st->channels[channel].cfg.odr)
335 st->channels[channel].cfg.live = false;
336
337 st->channels[channel].cfg.filter_type = new_filter;
338 st->channels[channel].cfg.odr = new_odr;
339 }
340
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)341 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
342 struct ad7124_channel_config *cfg)
343 {
344 struct ad7124_channel_config *cfg_aux;
345 int i;
346
347 /*
348 * This is just to make sure that the comparison is adapted after
349 * struct ad7124_channel_config was changed.
350 */
351 static_assert(sizeof_field(struct ad7124_channel_config, config_props) ==
352 sizeof(struct {
353 enum ad7124_ref_sel refsel;
354 bool bipolar;
355 bool buf_positive;
356 bool buf_negative;
357 unsigned int vref_mv;
358 unsigned int pga_bits;
359 unsigned int odr;
360 unsigned int odr_sel_bits;
361 unsigned int filter_type;
362 }));
363
364 for (i = 0; i < st->num_channels; i++) {
365 cfg_aux = &st->channels[i].cfg;
366
367 if (cfg_aux->live &&
368 cfg->refsel == cfg_aux->refsel &&
369 cfg->bipolar == cfg_aux->bipolar &&
370 cfg->buf_positive == cfg_aux->buf_positive &&
371 cfg->buf_negative == cfg_aux->buf_negative &&
372 cfg->vref_mv == cfg_aux->vref_mv &&
373 cfg->pga_bits == cfg_aux->pga_bits &&
374 cfg->odr == cfg_aux->odr &&
375 cfg->odr_sel_bits == cfg_aux->odr_sel_bits &&
376 cfg->filter_type == cfg_aux->filter_type)
377 return cfg_aux;
378 }
379
380 return NULL;
381 }
382
ad7124_find_free_config_slot(struct ad7124_state * st)383 static int ad7124_find_free_config_slot(struct ad7124_state *st)
384 {
385 unsigned int free_cfg_slot;
386
387 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
388 if (free_cfg_slot == AD7124_MAX_CONFIGS)
389 return -1;
390
391 return free_cfg_slot;
392 }
393
394 /* Only called during probe, so dev_err_probe() can be used */
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)395 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
396 {
397 struct device *dev = &st->sd.spi->dev;
398 unsigned int refsel = cfg->refsel;
399
400 switch (refsel) {
401 case AD7124_REFIN1:
402 case AD7124_REFIN2:
403 case AD7124_AVDD_REF:
404 if (IS_ERR(st->vref[refsel]))
405 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]),
406 "Error, trying to use external voltage reference without a %s regulator.\n",
407 ad7124_ref_names[refsel]);
408
409 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
410 /* Conversion from uV to mV */
411 cfg->vref_mv /= 1000;
412 return 0;
413 case AD7124_INT_REF:
414 cfg->vref_mv = 2500;
415 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
416 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
417 return 0;
418 default:
419 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel);
420 }
421 }
422
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)423 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
424 unsigned int cfg_slot)
425 {
426 unsigned int tmp;
427 unsigned int val;
428 int ret;
429
430 cfg->cfg_slot = cfg_slot;
431
432 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
433 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
434 AD7124_CONFIG_IN_BUFF(tmp) | AD7124_CONFIG_PGA(cfg->pga_bits);
435
436 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
437 if (ret < 0)
438 return ret;
439
440 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type) |
441 AD7124_FILTER_FS(cfg->odr_sel_bits);
442 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot),
443 AD7124_FILTER_TYPE_MSK | AD7124_FILTER_FS_MSK,
444 tmp, 3);
445 }
446
ad7124_pop_config(struct ad7124_state * st)447 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
448 {
449 struct ad7124_channel_config *lru_cfg;
450 struct ad7124_channel_config *cfg;
451 int ret;
452 int i;
453
454 /*
455 * Pop least recently used config from the fifo
456 * in order to make room for the new one
457 */
458 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
459 if (ret <= 0)
460 return NULL;
461
462 lru_cfg->live = false;
463
464 /* mark slot as free */
465 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
466
467 /* invalidate all other configs that pointed to this one */
468 for (i = 0; i < st->num_channels; i++) {
469 cfg = &st->channels[i].cfg;
470
471 if (cfg->cfg_slot == lru_cfg->cfg_slot)
472 cfg->live = false;
473 }
474
475 return lru_cfg;
476 }
477
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)478 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
479 {
480 struct ad7124_channel_config *lru_cfg;
481 int free_cfg_slot;
482
483 free_cfg_slot = ad7124_find_free_config_slot(st);
484 if (free_cfg_slot >= 0) {
485 /* push the new config in configs queue */
486 kfifo_put(&st->live_cfgs_fifo, cfg);
487 } else {
488 /* pop one config to make room for the new one */
489 lru_cfg = ad7124_pop_config(st);
490 if (!lru_cfg)
491 return -EINVAL;
492
493 /* push the new config in configs queue */
494 free_cfg_slot = lru_cfg->cfg_slot;
495 kfifo_put(&st->live_cfgs_fifo, cfg);
496 }
497
498 /* mark slot as used */
499 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
500
501 return ad7124_write_config(st, cfg, free_cfg_slot);
502 }
503
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)504 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
505 {
506 ch->cfg.live = true;
507 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
508 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
509 }
510
ad7124_prepare_read(struct ad7124_state * st,int address)511 static int ad7124_prepare_read(struct ad7124_state *st, int address)
512 {
513 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
514 struct ad7124_channel_config *live_cfg;
515
516 /*
517 * Before doing any reads assign the channel a configuration.
518 * Check if channel's config is on the device
519 */
520 if (!cfg->live) {
521 /* check if config matches another one */
522 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
523 if (!live_cfg)
524 ad7124_push_config(st, cfg);
525 else
526 cfg->cfg_slot = live_cfg->cfg_slot;
527 }
528
529 /* point channel to the config slot and enable */
530 return ad7124_enable_channel(st, &st->channels[address]);
531 }
532
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)533 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
534 {
535 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
536
537 return ad7124_prepare_read(st, channel);
538 }
539
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)540 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
541 {
542 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
543 int ret;
544
545 mutex_lock(&st->cfgs_lock);
546 ret = __ad7124_set_channel(sd, channel);
547 mutex_unlock(&st->cfgs_lock);
548
549 return ret;
550 }
551
ad7124_append_status(struct ad_sigma_delta * sd,bool append)552 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
553 {
554 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
555 unsigned int adc_control = st->adc_control;
556 int ret;
557
558 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
559 adc_control |= AD7124_ADC_STATUS_EN(append);
560
561 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
562 if (ret < 0)
563 return ret;
564
565 st->adc_control = adc_control;
566
567 return 0;
568 }
569
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)570 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
571 {
572 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
573
574 /* The relevant thing here is that AD7124_CHANNEL_EN_MSK is cleared. */
575 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0);
576 }
577
ad7124_disable_all(struct ad_sigma_delta * sd)578 static int ad7124_disable_all(struct ad_sigma_delta *sd)
579 {
580 int ret;
581 int i;
582
583 for (i = 0; i < 16; i++) {
584 ret = ad7124_disable_one(sd, i);
585 if (ret < 0)
586 return ret;
587 }
588
589 return 0;
590 }
591
592 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
593 .set_channel = ad7124_set_channel,
594 .append_status = ad7124_append_status,
595 .disable_all = ad7124_disable_all,
596 .disable_one = ad7124_disable_one,
597 .set_mode = ad7124_set_mode,
598 .has_registers = true,
599 .addr_shift = 0,
600 .read_mask = BIT(6),
601 .status_ch_mask = GENMASK(3, 0),
602 .data_reg = AD7124_DATA,
603 .num_slots = 8,
604 .irq_flags = IRQF_TRIGGER_FALLING,
605 .num_resetclks = 64,
606 };
607
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)608 static int ad7124_read_raw(struct iio_dev *indio_dev,
609 struct iio_chan_spec const *chan,
610 int *val, int *val2, long info)
611 {
612 struct ad7124_state *st = iio_priv(indio_dev);
613 int idx, ret;
614
615 switch (info) {
616 case IIO_CHAN_INFO_RAW:
617 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
618 if (ret < 0)
619 return ret;
620
621 return IIO_VAL_INT;
622 case IIO_CHAN_INFO_SCALE:
623 switch (chan->type) {
624 case IIO_VOLTAGE:
625 mutex_lock(&st->cfgs_lock);
626
627 idx = st->channels[chan->address].cfg.pga_bits;
628 *val = st->channels[chan->address].cfg.vref_mv;
629 if (st->channels[chan->address].cfg.bipolar)
630 *val2 = chan->scan_type.realbits - 1 + idx;
631 else
632 *val2 = chan->scan_type.realbits + idx;
633
634 mutex_unlock(&st->cfgs_lock);
635 return IIO_VAL_FRACTIONAL_LOG2;
636
637 case IIO_TEMP:
638 /*
639 * According to the data sheet
640 * Temperature (°C)
641 * = ((Conversion − 0x800000)/13584) − 272.5
642 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584
643 * = (Conversion − 12090248) / 13584
644 * So scale with 1000/13584 to yield °mC. Reduce by 8 to
645 * 125/1698.
646 */
647 *val = 125;
648 *val2 = 1698;
649 return IIO_VAL_FRACTIONAL;
650
651 default:
652 return -EINVAL;
653 }
654
655 case IIO_CHAN_INFO_OFFSET:
656 switch (chan->type) {
657 case IIO_VOLTAGE:
658 mutex_lock(&st->cfgs_lock);
659 if (st->channels[chan->address].cfg.bipolar)
660 *val = -(1 << (chan->scan_type.realbits - 1));
661 else
662 *val = 0;
663
664 mutex_unlock(&st->cfgs_lock);
665 return IIO_VAL_INT;
666
667 case IIO_TEMP:
668 /* see calculation above */
669 *val = -12090248;
670 return IIO_VAL_INT;
671
672 default:
673 return -EINVAL;
674 }
675
676 case IIO_CHAN_INFO_SAMP_FREQ:
677 mutex_lock(&st->cfgs_lock);
678 *val = st->channels[chan->address].cfg.odr;
679 mutex_unlock(&st->cfgs_lock);
680
681 return IIO_VAL_INT;
682 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
683 mutex_lock(&st->cfgs_lock);
684 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
685 mutex_unlock(&st->cfgs_lock);
686
687 return IIO_VAL_INT;
688 default:
689 return -EINVAL;
690 }
691 }
692
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)693 static int ad7124_write_raw(struct iio_dev *indio_dev,
694 struct iio_chan_spec const *chan,
695 int val, int val2, long info)
696 {
697 struct ad7124_state *st = iio_priv(indio_dev);
698 unsigned int res, gain, full_scale, vref;
699 int ret = 0;
700
701 mutex_lock(&st->cfgs_lock);
702
703 switch (info) {
704 case IIO_CHAN_INFO_SAMP_FREQ:
705 if (val2 != 0 || val == 0) {
706 ret = -EINVAL;
707 break;
708 }
709
710 ad7124_set_channel_odr(st, chan->address, val);
711 break;
712 case IIO_CHAN_INFO_SCALE:
713 if (val != 0) {
714 ret = -EINVAL;
715 break;
716 }
717
718 if (st->channels[chan->address].cfg.bipolar)
719 full_scale = 1 << (chan->scan_type.realbits - 1);
720 else
721 full_scale = 1 << chan->scan_type.realbits;
722
723 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
724 res = DIV_ROUND_CLOSEST(vref, full_scale);
725 gain = DIV_ROUND_CLOSEST(res, val2);
726 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
727
728 if (st->channels[chan->address].cfg.pga_bits != res)
729 st->channels[chan->address].cfg.live = false;
730
731 st->channels[chan->address].cfg.pga_bits = res;
732 break;
733 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
734 if (val2 != 0) {
735 ret = -EINVAL;
736 break;
737 }
738
739 ad7124_set_3db_filter_freq(st, chan->address, val);
740 break;
741 default:
742 ret = -EINVAL;
743 }
744
745 mutex_unlock(&st->cfgs_lock);
746 return ret;
747 }
748
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)749 static int ad7124_reg_access(struct iio_dev *indio_dev,
750 unsigned int reg,
751 unsigned int writeval,
752 unsigned int *readval)
753 {
754 struct ad7124_state *st = iio_priv(indio_dev);
755 int ret;
756
757 if (reg >= ARRAY_SIZE(ad7124_reg_size))
758 return -EINVAL;
759
760 if (readval)
761 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
762 readval);
763 else
764 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
765 writeval);
766
767 return ret;
768 }
769
770 static IIO_CONST_ATTR(in_voltage_scale_available,
771 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
772
773 static struct attribute *ad7124_attributes[] = {
774 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
775 NULL,
776 };
777
778 static const struct attribute_group ad7124_attrs_group = {
779 .attrs = ad7124_attributes,
780 };
781
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)782 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
783 const unsigned long *scan_mask)
784 {
785 struct ad7124_state *st = iio_priv(indio_dev);
786 bool bit_set;
787 int ret;
788 int i;
789
790 mutex_lock(&st->cfgs_lock);
791 for (i = 0; i < st->num_channels; i++) {
792 bit_set = test_bit(i, scan_mask);
793 if (bit_set)
794 ret = __ad7124_set_channel(&st->sd, i);
795 else
796 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
797 0, 2);
798 if (ret < 0) {
799 mutex_unlock(&st->cfgs_lock);
800
801 return ret;
802 }
803 }
804
805 mutex_unlock(&st->cfgs_lock);
806
807 return 0;
808 }
809
810 static const struct iio_info ad7124_info = {
811 .read_raw = ad7124_read_raw,
812 .write_raw = ad7124_write_raw,
813 .debugfs_reg_access = &ad7124_reg_access,
814 .validate_trigger = ad_sd_validate_trigger,
815 .update_scan_mode = ad7124_update_scan_mode,
816 .attrs = &ad7124_attrs_group,
817 };
818
819 /* Only called during probe, so dev_err_probe() can be used */
ad7124_soft_reset(struct ad7124_state * st)820 static int ad7124_soft_reset(struct ad7124_state *st)
821 {
822 struct device *dev = &st->sd.spi->dev;
823 unsigned int readval, timeout;
824 int ret;
825
826 ret = ad_sd_reset(&st->sd);
827 if (ret < 0)
828 return ret;
829
830 fsleep(200);
831 timeout = 100;
832 do {
833 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
834 if (ret < 0)
835 return dev_err_probe(dev, ret, "Error reading status register\n");
836
837 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
838 return 0;
839
840 /* The AD7124 requires typically 2ms to power up and settle */
841 usleep_range(100, 2000);
842 } while (--timeout);
843
844 return dev_err_probe(dev, -EIO, "Soft reset failed\n");
845 }
846
ad7124_check_chip_id(struct ad7124_state * st)847 static int ad7124_check_chip_id(struct ad7124_state *st)
848 {
849 struct device *dev = &st->sd.spi->dev;
850 unsigned int readval, chip_id, silicon_rev;
851 int ret;
852
853 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
854 if (ret < 0)
855 return dev_err_probe(dev, ret, "Failure to read ID register\n");
856
857 chip_id = AD7124_DEVICE_ID_GET(readval);
858 silicon_rev = AD7124_SILICON_REV_GET(readval);
859
860 if (chip_id != st->chip_info->chip_id)
861 return dev_err_probe(dev, -ENODEV,
862 "Chip ID mismatch: expected %u, got %u\n",
863 st->chip_info->chip_id, chip_id);
864
865 if (silicon_rev == 0)
866 return dev_err_probe(dev, -ENODEV,
867 "Silicon revision empty. Chip may not be present\n");
868
869 return 0;
870 }
871
872 /*
873 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4
874 * while they are fine for ad7124-8. Values above 31 don't fit
875 * into the register field and so are invalid for sure.
876 */
ad7124_valid_input_select(unsigned int ain,const struct ad7124_chip_info * info)877 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info)
878 {
879 if (ain >= info->num_inputs && ain < 16)
880 return false;
881
882 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM_MSK);
883 }
884
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)885 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
886 struct device *dev)
887 {
888 struct ad7124_state *st = iio_priv(indio_dev);
889 struct ad7124_channel_config *cfg;
890 struct ad7124_channel *channels;
891 struct iio_chan_spec *chan;
892 unsigned int ain[2], channel = 0, tmp;
893 unsigned int num_channels;
894 int ret;
895
896 num_channels = device_get_child_node_count(dev);
897
898 /*
899 * The driver assigns each logical channel defined in the device tree
900 * statically one channel register. So only accept 16 such logical
901 * channels to not treat CONFIG_0 (i.e. the register following
902 * CHANNEL_15) as an additional channel register. The driver could be
903 * improved to lift this limitation.
904 */
905 if (num_channels > AD7124_MAX_CHANNELS)
906 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n");
907
908 /* Add one for temperature */
909 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS);
910
911 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
912 sizeof(*chan), GFP_KERNEL);
913 if (!chan)
914 return -ENOMEM;
915
916 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
917 GFP_KERNEL);
918 if (!channels)
919 return -ENOMEM;
920
921 indio_dev->channels = chan;
922 indio_dev->num_channels = st->num_channels;
923 st->channels = channels;
924
925 device_for_each_child_node_scoped(dev, child) {
926 ret = fwnode_property_read_u32(child, "reg", &channel);
927 if (ret)
928 return dev_err_probe(dev, ret,
929 "Failed to parse reg property of %pfwP\n", child);
930
931 if (channel >= num_channels)
932 return dev_err_probe(dev, -EINVAL,
933 "Channel index >= number of channels in %pfwP\n", child);
934
935 ret = fwnode_property_read_u32_array(child, "diff-channels",
936 ain, 2);
937 if (ret)
938 return dev_err_probe(dev, ret,
939 "Failed to parse diff-channels property of %pfwP\n", child);
940
941 if (!ad7124_valid_input_select(ain[0], st->chip_info) ||
942 !ad7124_valid_input_select(ain[1], st->chip_info))
943 return dev_err_probe(dev, -EINVAL,
944 "diff-channels property of %pfwP contains invalid data\n", child);
945
946 st->channels[channel].nr = channel;
947 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
948 AD7124_CHANNEL_AINM(ain[1]);
949
950 cfg = &st->channels[channel].cfg;
951 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
952
953 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
954 if (ret)
955 cfg->refsel = AD7124_INT_REF;
956 else
957 cfg->refsel = tmp;
958
959 cfg->buf_positive =
960 fwnode_property_read_bool(child, "adi,buffered-positive");
961 cfg->buf_negative =
962 fwnode_property_read_bool(child, "adi,buffered-negative");
963
964 chan[channel] = ad7124_channel_template;
965 chan[channel].address = channel;
966 chan[channel].scan_index = channel;
967 chan[channel].channel = ain[0];
968 chan[channel].channel2 = ain[1];
969 }
970
971 if (num_channels < AD7124_MAX_CHANNELS) {
972 st->channels[num_channels] = (struct ad7124_channel) {
973 .nr = num_channels,
974 .ain = AD7124_CHANNEL_AINP(AD7124_INPUT_TEMPSENSOR) |
975 AD7124_CHANNEL_AINM(AD7124_INPUT_AVSS),
976 .cfg = {
977 .bipolar = true,
978 },
979 };
980
981 chan[num_channels] = (struct iio_chan_spec) {
982 .type = IIO_TEMP,
983 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
984 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
985 BIT(IIO_CHAN_INFO_SAMP_FREQ),
986 .scan_type = {
987 /*
988 * You might find it strange that a bipolar
989 * measurement yields an unsigned value, but
990 * this matches the device's manual.
991 */
992 .sign = 'u',
993 .realbits = 24,
994 .storagebits = 32,
995 .endianness = IIO_BE,
996 },
997 .address = num_channels,
998 .scan_index = num_channels,
999 };
1000 }
1001
1002 return 0;
1003 }
1004
ad7124_setup(struct ad7124_state * st)1005 static int ad7124_setup(struct ad7124_state *st)
1006 {
1007 struct device *dev = &st->sd.spi->dev;
1008 unsigned int fclk, power_mode;
1009 int i, ret;
1010
1011 fclk = clk_get_rate(st->mclk);
1012 if (!fclk)
1013 return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n");
1014
1015 /* The power mode changes the master clock frequency */
1016 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
1017 ARRAY_SIZE(ad7124_master_clk_freq_hz),
1018 fclk);
1019 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
1020 ret = clk_set_rate(st->mclk, fclk);
1021 if (ret)
1022 return dev_err_probe(dev, ret, "Failed to set mclk rate\n");
1023 }
1024
1025 /* Set the power mode */
1026 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
1027 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
1028
1029 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
1030 st->adc_control |= AD7124_ADC_CTRL_MODE(AD_SD_MODE_IDLE);
1031
1032 mutex_init(&st->cfgs_lock);
1033 INIT_KFIFO(st->live_cfgs_fifo);
1034 for (i = 0; i < st->num_channels; i++) {
1035
1036 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
1037 if (ret < 0)
1038 return ret;
1039
1040 /*
1041 * 9.38 SPS is the minimum output data rate supported
1042 * regardless of the selected power mode. Round it up to 10 and
1043 * set all channels to this default value.
1044 */
1045 ad7124_set_channel_odr(st, i, 10);
1046 }
1047
1048 ad7124_disable_all(&st->sd);
1049
1050 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
1051 if (ret < 0)
1052 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n");
1053
1054 return ret;
1055 }
1056
ad7124_reg_disable(void * r)1057 static void ad7124_reg_disable(void *r)
1058 {
1059 regulator_disable(r);
1060 }
1061
ad7124_probe(struct spi_device * spi)1062 static int ad7124_probe(struct spi_device *spi)
1063 {
1064 const struct ad7124_chip_info *info;
1065 struct device *dev = &spi->dev;
1066 struct ad7124_state *st;
1067 struct iio_dev *indio_dev;
1068 int i, ret;
1069
1070 info = spi_get_device_match_data(spi);
1071 if (!info)
1072 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n");
1073
1074 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1075 if (!indio_dev)
1076 return -ENOMEM;
1077
1078 st = iio_priv(indio_dev);
1079
1080 st->chip_info = info;
1081
1082 indio_dev->name = st->chip_info->name;
1083 indio_dev->modes = INDIO_DIRECT_MODE;
1084 indio_dev->info = &ad7124_info;
1085
1086 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
1087 if (ret < 0)
1088 return ret;
1089
1090 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
1091 if (ret < 0)
1092 return ret;
1093
1094 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
1095 if (i == AD7124_INT_REF)
1096 continue;
1097
1098 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1099 ad7124_ref_names[i]);
1100 if (PTR_ERR(st->vref[i]) == -ENODEV)
1101 continue;
1102 else if (IS_ERR(st->vref[i]))
1103 return PTR_ERR(st->vref[i]);
1104
1105 ret = regulator_enable(st->vref[i]);
1106 if (ret)
1107 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i);
1108
1109 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1110 st->vref[i]);
1111 if (ret)
1112 return dev_err_probe(dev, ret, "Failed to register disable handler for regulator #%d\n", i);
1113 }
1114
1115 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
1116 if (IS_ERR(st->mclk))
1117 return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get mclk\n");
1118
1119 ret = ad7124_soft_reset(st);
1120 if (ret < 0)
1121 return ret;
1122
1123 ret = ad7124_check_chip_id(st);
1124 if (ret)
1125 return ret;
1126
1127 ret = ad7124_setup(st);
1128 if (ret < 0)
1129 return ret;
1130
1131 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1132 if (ret < 0)
1133 return dev_err_probe(dev, ret, "Failed to setup triggers\n");
1134
1135 ret = devm_iio_device_register(&spi->dev, indio_dev);
1136 if (ret < 0)
1137 return dev_err_probe(dev, ret, "Failed to register iio device\n");
1138
1139 return 0;
1140 }
1141
1142 static const struct of_device_id ad7124_of_match[] = {
1143 { .compatible = "adi,ad7124-4",
1144 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1145 { .compatible = "adi,ad7124-8",
1146 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1147 { }
1148 };
1149 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1150
1151 static const struct spi_device_id ad71124_ids[] = {
1152 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1153 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1154 { }
1155 };
1156 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1157
1158 static struct spi_driver ad71124_driver = {
1159 .driver = {
1160 .name = "ad7124",
1161 .of_match_table = ad7124_of_match,
1162 },
1163 .probe = ad7124_probe,
1164 .id_table = ad71124_ids,
1165 };
1166 module_spi_driver(ad71124_driver);
1167
1168 MODULE_AUTHOR("Stefan Popa <[email protected]>");
1169 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1170 MODULE_LICENSE("GPL");
1171 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1172