1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Renesas Versaclock 3
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/i2c.h>
10 #include <linux/limits.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13
14 #define NUM_CONFIG_REGISTERS 37
15
16 #define VC3_GENERAL_CTR 0x0
17 #define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3)
18 #define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2)
19
20 #define VC3_PLL3_M_DIVIDER 0x3
21 #define VC3_PLL3_M_DIV1 BIT(7)
22 #define VC3_PLL3_M_DIV2 BIT(6)
23 #define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0))
24
25 #define VC3_PLL3_N_DIVIDER 0x4
26 #define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5
27
28 #define VC3_PLL3_CHARGE_PUMP_CTRL 0x6
29 #define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7)
30
31 #define VC3_PLL1_CTRL_OUTDIV5 0x7
32 #define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7)
33
34 #define VC3_PLL1_M_DIVIDER 0x8
35 #define VC3_PLL1_M_DIV1 BIT(7)
36 #define VC3_PLL1_M_DIV2 BIT(6)
37 #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))
38
39 #define VC3_PLL1_VCO_N_DIVIDER 0x9
40 #define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa
41
42 #define VC3_OUT_DIV1_DIV2_CTRL 0xf
43
44 #define VC3_PLL2_FB_INT_DIV_MSB 0x10
45 #define VC3_PLL2_FB_INT_DIV_LSB 0x11
46 #define VC3_PLL2_FB_FRC_DIV_MSB 0x12
47 #define VC3_PLL2_FB_FRC_DIV_LSB 0x13
48
49 #define VC3_PLL2_M_DIVIDER 0x1a
50 #define VC3_PLL2_MDIV_DOUBLER BIT(7)
51 #define VC3_PLL2_M_DIV1 BIT(6)
52 #define VC3_PLL2_M_DIV2 BIT(5)
53 #define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0))
54
55 #define VC3_OUT_DIV3_DIV4_CTRL 0x1b
56
57 #define VC3_PLL_OP_CTRL 0x1c
58 #define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6
59
60 #define VC3_OUTPUT_CTR 0x1d
61 #define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
62
63 #define VC3_SE2_CTRL_REG0 0x1f
64 #define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
65
66 #define VC3_SE3_DIFF1_CTRL_REG 0x21
67 #define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
68
69 #define VC3_DIFF1_CTRL_REG 0x22
70 #define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7)
71
72 #define VC3_DIFF2_CTRL_REG 0x23
73 #define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7)
74
75 #define VC3_SE1_DIV4_CTRL 0x24
76 #define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3)
77
78 #define VC3_PLL1_VCO_MIN 300000000UL
79 #define VC3_PLL1_VCO_MAX 600000000UL
80
81 #define VC3_PLL3_VCO_MIN 300000000UL
82 #define VC3_PLL3_VCO_MAX 800000000UL
83
84 #define VC3_2_POW_16 (U16_MAX + 1)
85 #define VC3_DIV_MASK(width) ((1 << (width)) - 1)
86
87 enum vc3_pfd_mux {
88 VC3_PFD2_MUX,
89 VC3_PFD3_MUX,
90 };
91
92 enum vc3_pfd {
93 VC3_PFD1,
94 VC3_PFD2,
95 VC3_PFD3,
96 };
97
98 enum vc3_pll {
99 VC3_PLL1,
100 VC3_PLL2,
101 VC3_PLL3,
102 };
103
104 enum vc3_div_mux {
105 VC3_DIV1_MUX,
106 VC3_DIV3_MUX,
107 VC3_DIV4_MUX,
108 };
109
110 enum vc3_div {
111 VC3_DIV1,
112 VC3_DIV2,
113 VC3_DIV3,
114 VC3_DIV4,
115 VC3_DIV5,
116 };
117
118 enum vc3_clk {
119 VC3_REF,
120 VC3_SE1,
121 VC3_SE2,
122 VC3_SE3,
123 VC3_DIFF1,
124 VC3_DIFF2,
125 };
126
127 enum vc3_clk_mux {
128 VC3_SE1_MUX = VC3_SE1 - 1,
129 VC3_SE2_MUX = VC3_SE2 - 1,
130 VC3_SE3_MUX = VC3_SE3 - 1,
131 VC3_DIFF1_MUX = VC3_DIFF1 - 1,
132 VC3_DIFF2_MUX = VC3_DIFF2 - 1,
133 };
134
135 struct vc3_clk_data {
136 u8 offs;
137 u8 bitmsk;
138 };
139
140 struct vc3_pfd_data {
141 u8 num;
142 u8 offs;
143 u8 mdiv1_bitmsk;
144 u8 mdiv2_bitmsk;
145 };
146
147 struct vc3_vco {
148 unsigned long min;
149 unsigned long max;
150 };
151
152 struct vc3_pll_data {
153 struct vc3_vco vco;
154 u8 num;
155 u8 int_div_msb_offs;
156 u8 int_div_lsb_offs;
157 };
158
159 struct vc3_div_data {
160 const struct clk_div_table *table;
161 u8 offs;
162 u8 shift;
163 u8 width;
164 u8 flags;
165 };
166
167 struct vc3_hw_data {
168 struct clk_hw hw;
169 struct regmap *regmap;
170 void *data;
171
172 u32 div_int;
173 u32 div_frc;
174 };
175
176 struct vc3_hw_cfg {
177 struct vc3_vco pll2_vco;
178 u32 se2_clk_sel_msk;
179 };
180
181 static const struct clk_div_table div1_divs[] = {
182 { .val = 0, .div = 1, }, { .val = 1, .div = 4, },
183 { .val = 2, .div = 5, }, { .val = 3, .div = 6, },
184 { .val = 4, .div = 2, }, { .val = 5, .div = 8, },
185 { .val = 6, .div = 10, }, { .val = 7, .div = 12, },
186 { .val = 8, .div = 4, }, { .val = 9, .div = 16, },
187 { .val = 10, .div = 20, }, { .val = 11, .div = 24, },
188 { .val = 12, .div = 8, }, { .val = 13, .div = 32, },
189 { .val = 14, .div = 40, }, { .val = 15, .div = 48, },
190 {}
191 };
192
193 static const struct clk_div_table div245_divs[] = {
194 { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
195 { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
196 { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
197 { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
198 { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
199 { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
200 { .val = 12, .div = 5, }, { .val = 13, .div = 15, },
201 { .val = 14, .div = 25, }, { .val = 15, .div = 50, },
202 {}
203 };
204
205 static const struct clk_div_table div3_divs[] = {
206 { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
207 { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
208 { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
209 { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
210 { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
211 { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
212 { .val = 12, .div = 8, }, { .val = 13, .div = 24, },
213 { .val = 14, .div = 40, }, { .val = 15, .div = 80, },
214 {}
215 };
216
217 static struct clk_hw *clk_out[6];
218
vc3_pfd_mux_get_parent(struct clk_hw * hw)219 static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw)
220 {
221 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
222 const struct vc3_clk_data *pfd_mux = vc3->data;
223 u32 src;
224
225 regmap_read(vc3->regmap, pfd_mux->offs, &src);
226
227 return !!(src & pfd_mux->bitmsk);
228 }
229
vc3_pfd_mux_set_parent(struct clk_hw * hw,u8 index)230 static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index)
231 {
232 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
233 const struct vc3_clk_data *pfd_mux = vc3->data;
234
235 return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk,
236 index ? pfd_mux->bitmsk : 0);
237 }
238
239 static const struct clk_ops vc3_pfd_mux_ops = {
240 .determine_rate = clk_hw_determine_rate_no_reparent,
241 .set_parent = vc3_pfd_mux_set_parent,
242 .get_parent = vc3_pfd_mux_get_parent,
243 };
244
vc3_pfd_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)245 static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
246 unsigned long parent_rate)
247 {
248 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
249 const struct vc3_pfd_data *pfd = vc3->data;
250 unsigned int prediv, premul;
251 unsigned long rate;
252 u8 mdiv;
253
254 regmap_read(vc3->regmap, pfd->offs, &prediv);
255 if (pfd->num == VC3_PFD1) {
256 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
257 if (prediv & pfd->mdiv1_bitmsk) {
258 /* check doubler is set or not */
259 regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul);
260 if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
261 parent_rate *= 2;
262 return parent_rate;
263 }
264 mdiv = VC3_PLL1_M_DIV(prediv);
265 } else if (pfd->num == VC3_PFD2) {
266 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
267 if (prediv & pfd->mdiv1_bitmsk) {
268 regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul);
269 /* check doubler is set or not */
270 if (premul & VC3_PLL2_MDIV_DOUBLER)
271 parent_rate *= 2;
272 return parent_rate;
273 }
274
275 mdiv = VC3_PLL2_M_DIV(prediv);
276 } else {
277 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
278 if (prediv & pfd->mdiv1_bitmsk)
279 return parent_rate;
280
281 mdiv = VC3_PLL3_M_DIV(prediv);
282 }
283
284 if (prediv & pfd->mdiv2_bitmsk)
285 rate = parent_rate / 2;
286 else
287 rate = parent_rate / mdiv;
288
289 return rate;
290 }
291
vc3_pfd_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)292 static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
293 unsigned long *parent_rate)
294 {
295 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
296 const struct vc3_pfd_data *pfd = vc3->data;
297 unsigned long idiv;
298
299 /* PLL cannot operate with input clock above 50 MHz. */
300 if (rate > 50000000)
301 return -EINVAL;
302
303 /* CLKIN within range of PLL input, feed directly to PLL. */
304 if (*parent_rate <= 50000000)
305 return *parent_rate;
306
307 idiv = DIV_ROUND_UP(*parent_rate, rate);
308 if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) {
309 if (idiv > 63)
310 return -EINVAL;
311 } else {
312 if (idiv > 31)
313 return -EINVAL;
314 }
315
316 return *parent_rate / idiv;
317 }
318
vc3_pfd_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)319 static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
320 unsigned long parent_rate)
321 {
322 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
323 const struct vc3_pfd_data *pfd = vc3->data;
324 unsigned long idiv;
325 u8 div;
326
327 /* CLKIN within range of PLL input, feed directly to PLL. */
328 if (parent_rate <= 50000000) {
329 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
330 pfd->mdiv1_bitmsk);
331 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0);
332 return 0;
333 }
334
335 idiv = DIV_ROUND_UP(parent_rate, rate);
336 /* We have dedicated div-2 predivider. */
337 if (idiv == 2) {
338 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk,
339 pfd->mdiv2_bitmsk);
340 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
341 } else {
342 if (pfd->num == VC3_PFD1)
343 div = VC3_PLL1_M_DIV(idiv);
344 else if (pfd->num == VC3_PFD2)
345 div = VC3_PLL2_M_DIV(idiv);
346 else
347 div = VC3_PLL3_M_DIV(idiv);
348
349 regmap_write(vc3->regmap, pfd->offs, div);
350 }
351
352 return 0;
353 }
354
355 static const struct clk_ops vc3_pfd_ops = {
356 .recalc_rate = vc3_pfd_recalc_rate,
357 .round_rate = vc3_pfd_round_rate,
358 .set_rate = vc3_pfd_set_rate,
359 };
360
vc3_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)361 static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw,
362 unsigned long parent_rate)
363 {
364 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
365 const struct vc3_pll_data *pll = vc3->data;
366 u32 div_int, div_frc, val;
367 unsigned long rate;
368
369 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
370 div_int = (val & GENMASK(2, 0)) << 8;
371 regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val);
372 div_int |= val;
373
374 if (pll->num == VC3_PLL2) {
375 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val);
376 div_frc = val << 8;
377 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val);
378 div_frc |= val;
379 rate = (parent_rate *
380 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
381 } else {
382 rate = parent_rate * div_int;
383 }
384
385 return rate;
386 }
387
vc3_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)388 static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
389 unsigned long *parent_rate)
390 {
391 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
392 const struct vc3_pll_data *pll = vc3->data;
393 u64 div_frc;
394
395 if (rate < pll->vco.min)
396 rate = pll->vco.min;
397 if (rate > pll->vco.max)
398 rate = pll->vco.max;
399
400 vc3->div_int = rate / *parent_rate;
401
402 if (pll->num == VC3_PLL2) {
403 if (vc3->div_int > 0x7ff)
404 rate = *parent_rate * 0x7ff;
405
406 /* Determine best fractional part, which is 16 bit wide */
407 div_frc = rate % *parent_rate;
408 div_frc *= BIT(16) - 1;
409
410 vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX);
411 rate = (*parent_rate *
412 (vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16);
413 } else {
414 rate = *parent_rate * vc3->div_int;
415 }
416
417 return rate;
418 }
419
vc3_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)420 static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long parent_rate)
422 {
423 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
424 const struct vc3_pll_data *pll = vc3->data;
425 u32 val;
426
427 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
428 val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7);
429 regmap_write(vc3->regmap, pll->int_div_msb_offs, val);
430 regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff);
431
432 if (pll->num == VC3_PLL2) {
433 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB,
434 vc3->div_frc >> 8);
435 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB,
436 vc3->div_frc & 0xff);
437 }
438
439 return 0;
440 }
441
442 static const struct clk_ops vc3_pll_ops = {
443 .recalc_rate = vc3_pll_recalc_rate,
444 .round_rate = vc3_pll_round_rate,
445 .set_rate = vc3_pll_set_rate,
446 };
447
vc3_div_mux_get_parent(struct clk_hw * hw)448 static u8 vc3_div_mux_get_parent(struct clk_hw *hw)
449 {
450 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
451 const struct vc3_clk_data *div_mux = vc3->data;
452 u32 src;
453
454 regmap_read(vc3->regmap, div_mux->offs, &src);
455
456 return !!(src & div_mux->bitmsk);
457 }
458
vc3_div_mux_set_parent(struct clk_hw * hw,u8 index)459 static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index)
460 {
461 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
462 const struct vc3_clk_data *div_mux = vc3->data;
463
464 return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk,
465 index ? div_mux->bitmsk : 0);
466 }
467
468 static const struct clk_ops vc3_div_mux_ops = {
469 .determine_rate = clk_hw_determine_rate_no_reparent,
470 .set_parent = vc3_div_mux_set_parent,
471 .get_parent = vc3_div_mux_get_parent,
472 };
473
vc3_get_div(const struct clk_div_table * table,unsigned int val,unsigned long flag)474 static unsigned int vc3_get_div(const struct clk_div_table *table,
475 unsigned int val, unsigned long flag)
476 {
477 const struct clk_div_table *clkt;
478
479 for (clkt = table; clkt->div; clkt++)
480 if (clkt->val == val)
481 return clkt->div;
482
483 return 1;
484 }
485
vc3_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)486 static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,
487 unsigned long parent_rate)
488 {
489 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
490 const struct vc3_div_data *div_data = vc3->data;
491 unsigned int val;
492
493 regmap_read(vc3->regmap, div_data->offs, &val);
494 val >>= div_data->shift;
495 val &= VC3_DIV_MASK(div_data->width);
496
497 return divider_recalc_rate(hw, parent_rate, val, div_data->table,
498 div_data->flags, div_data->width);
499 }
500
vc3_div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)501 static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate,
502 unsigned long *parent_rate)
503 {
504 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
505 const struct vc3_div_data *div_data = vc3->data;
506 unsigned int bestdiv;
507
508 /* if read only, just return current value */
509 if (div_data->flags & CLK_DIVIDER_READ_ONLY) {
510 regmap_read(vc3->regmap, div_data->offs, &bestdiv);
511 bestdiv >>= div_data->shift;
512 bestdiv &= VC3_DIV_MASK(div_data->width);
513 bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags);
514 return DIV_ROUND_UP(*parent_rate, bestdiv);
515 }
516
517 return divider_round_rate(hw, rate, parent_rate, div_data->table,
518 div_data->width, div_data->flags);
519 }
520
vc3_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)521 static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,
522 unsigned long parent_rate)
523 {
524 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
525 const struct vc3_div_data *div_data = vc3->data;
526 unsigned int value;
527
528 value = divider_get_val(rate, parent_rate, div_data->table,
529 div_data->width, div_data->flags);
530 return regmap_update_bits(vc3->regmap, div_data->offs,
531 VC3_DIV_MASK(div_data->width) << div_data->shift,
532 value << div_data->shift);
533 }
534
535 static const struct clk_ops vc3_div_ops = {
536 .recalc_rate = vc3_div_recalc_rate,
537 .round_rate = vc3_div_round_rate,
538 .set_rate = vc3_div_set_rate,
539 };
540
vc3_clk_mux_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)541 static int vc3_clk_mux_determine_rate(struct clk_hw *hw,
542 struct clk_rate_request *req)
543 {
544 int frc;
545
546 if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) {
547 /* The below check is equivalent to (best_parent_rate/rate) */
548 if (req->best_parent_rate >= req->rate) {
549 frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate,
550 req->rate);
551 req->rate *= frc;
552 return clk_mux_determine_rate_flags(hw, req,
553 CLK_SET_RATE_PARENT);
554 }
555 }
556
557 return 0;
558 }
559
vc3_clk_mux_get_parent(struct clk_hw * hw)560 static u8 vc3_clk_mux_get_parent(struct clk_hw *hw)
561 {
562 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
563 const struct vc3_clk_data *clk_mux = vc3->data;
564 u32 val;
565
566 regmap_read(vc3->regmap, clk_mux->offs, &val);
567
568 return !!(val & clk_mux->bitmsk);
569 }
570
vc3_clk_mux_set_parent(struct clk_hw * hw,u8 index)571 static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)
572 {
573 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
574 const struct vc3_clk_data *clk_mux = vc3->data;
575
576 return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk,
577 index ? clk_mux->bitmsk : 0);
578 }
579
580 static const struct clk_ops vc3_clk_mux_ops = {
581 .determine_rate = vc3_clk_mux_determine_rate,
582 .set_parent = vc3_clk_mux_set_parent,
583 .get_parent = vc3_clk_mux_get_parent,
584 };
585
586 static const struct regmap_config vc3_regmap_config = {
587 .reg_bits = 8,
588 .val_bits = 8,
589 .cache_type = REGCACHE_MAPLE,
590 .max_register = 0x24,
591 };
592
593 static struct vc3_hw_data clk_div[5];
594
595 static const struct clk_parent_data pfd_mux_parent_data[] = {
596 { .index = 0, },
597 { .hw = &clk_div[VC3_DIV2].hw }
598 };
599
600 static struct vc3_hw_data clk_pfd_mux[] = {
601 [VC3_PFD2_MUX] = {
602 .data = &(struct vc3_clk_data) {
603 .offs = VC3_PLL_OP_CTRL,
604 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
605 },
606 .hw.init = &(struct clk_init_data) {
607 .name = "pfd2_mux",
608 .ops = &vc3_pfd_mux_ops,
609 .parent_data = pfd_mux_parent_data,
610 .num_parents = 2,
611 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
612 }
613 },
614 [VC3_PFD3_MUX] = {
615 .data = &(struct vc3_clk_data) {
616 .offs = VC3_GENERAL_CTR,
617 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
618 },
619 .hw.init = &(struct clk_init_data) {
620 .name = "pfd3_mux",
621 .ops = &vc3_pfd_mux_ops,
622 .parent_data = pfd_mux_parent_data,
623 .num_parents = 2,
624 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
625 }
626 }
627 };
628
629 static struct vc3_hw_data clk_pfd[] = {
630 [VC3_PFD1] = {
631 .data = &(struct vc3_pfd_data) {
632 .num = VC3_PFD1,
633 .offs = VC3_PLL1_M_DIVIDER,
634 .mdiv1_bitmsk = VC3_PLL1_M_DIV1,
635 .mdiv2_bitmsk = VC3_PLL1_M_DIV2
636 },
637 .hw.init = &(struct clk_init_data) {
638 .name = "pfd1",
639 .ops = &vc3_pfd_ops,
640 .parent_data = &(const struct clk_parent_data) {
641 .index = 0
642 },
643 .num_parents = 1,
644 .flags = CLK_SET_RATE_PARENT
645 }
646 },
647 [VC3_PFD2] = {
648 .data = &(struct vc3_pfd_data) {
649 .num = VC3_PFD2,
650 .offs = VC3_PLL2_M_DIVIDER,
651 .mdiv1_bitmsk = VC3_PLL2_M_DIV1,
652 .mdiv2_bitmsk = VC3_PLL2_M_DIV2
653 },
654 .hw.init = &(struct clk_init_data) {
655 .name = "pfd2",
656 .ops = &vc3_pfd_ops,
657 .parent_hws = (const struct clk_hw *[]) {
658 &clk_pfd_mux[VC3_PFD2_MUX].hw
659 },
660 .num_parents = 1,
661 .flags = CLK_SET_RATE_PARENT
662 }
663 },
664 [VC3_PFD3] = {
665 .data = &(struct vc3_pfd_data) {
666 .num = VC3_PFD3,
667 .offs = VC3_PLL3_M_DIVIDER,
668 .mdiv1_bitmsk = VC3_PLL3_M_DIV1,
669 .mdiv2_bitmsk = VC3_PLL3_M_DIV2
670 },
671 .hw.init = &(struct clk_init_data) {
672 .name = "pfd3",
673 .ops = &vc3_pfd_ops,
674 .parent_hws = (const struct clk_hw *[]) {
675 &clk_pfd_mux[VC3_PFD3_MUX].hw
676 },
677 .num_parents = 1,
678 .flags = CLK_SET_RATE_PARENT
679 }
680 }
681 };
682
683 static struct vc3_hw_data clk_pll[] = {
684 [VC3_PLL1] = {
685 .data = &(struct vc3_pll_data) {
686 .num = VC3_PLL1,
687 .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
688 .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
689 .vco = {
690 .min = VC3_PLL1_VCO_MIN,
691 .max = VC3_PLL1_VCO_MAX
692 }
693 },
694 .hw.init = &(struct clk_init_data) {
695 .name = "pll1",
696 .ops = &vc3_pll_ops,
697 .parent_hws = (const struct clk_hw *[]) {
698 &clk_pfd[VC3_PFD1].hw
699 },
700 .num_parents = 1,
701 .flags = CLK_SET_RATE_PARENT
702 }
703 },
704 [VC3_PLL2] = {
705 .data = &(struct vc3_pll_data) {
706 .num = VC3_PLL2,
707 .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
708 .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
709 },
710 .hw.init = &(struct clk_init_data) {
711 .name = "pll2",
712 .ops = &vc3_pll_ops,
713 .parent_hws = (const struct clk_hw *[]) {
714 &clk_pfd[VC3_PFD2].hw
715 },
716 .num_parents = 1,
717 .flags = CLK_SET_RATE_PARENT
718 }
719 },
720 [VC3_PLL3] = {
721 .data = &(struct vc3_pll_data) {
722 .num = VC3_PLL3,
723 .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
724 .int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
725 .vco = {
726 .min = VC3_PLL3_VCO_MIN,
727 .max = VC3_PLL3_VCO_MAX
728 }
729 },
730 .hw.init = &(struct clk_init_data) {
731 .name = "pll3",
732 .ops = &vc3_pll_ops,
733 .parent_hws = (const struct clk_hw *[]) {
734 &clk_pfd[VC3_PFD3].hw
735 },
736 .num_parents = 1,
737 .flags = CLK_SET_RATE_PARENT
738 }
739 }
740 };
741
742 static const struct clk_parent_data div_mux_parent_data[][2] = {
743 [VC3_DIV1_MUX] = {
744 { .hw = &clk_pll[VC3_PLL1].hw },
745 { .index = 0 }
746 },
747 [VC3_DIV3_MUX] = {
748 { .hw = &clk_pll[VC3_PLL2].hw },
749 { .hw = &clk_pll[VC3_PLL3].hw }
750 },
751 [VC3_DIV4_MUX] = {
752 { .hw = &clk_pll[VC3_PLL2].hw },
753 { .index = 0 }
754 }
755 };
756
757 static struct vc3_hw_data clk_div_mux[] = {
758 [VC3_DIV1_MUX] = {
759 .data = &(struct vc3_clk_data) {
760 .offs = VC3_GENERAL_CTR,
761 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
762 },
763 .hw.init = &(struct clk_init_data) {
764 .name = "div1_mux",
765 .ops = &vc3_div_mux_ops,
766 .parent_data = div_mux_parent_data[VC3_DIV1_MUX],
767 .num_parents = 2,
768 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
769 }
770 },
771 [VC3_DIV3_MUX] = {
772 .data = &(struct vc3_clk_data) {
773 .offs = VC3_PLL3_CHARGE_PUMP_CTRL,
774 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
775 },
776 .hw.init = &(struct clk_init_data) {
777 .name = "div3_mux",
778 .ops = &vc3_div_mux_ops,
779 .parent_data = div_mux_parent_data[VC3_DIV3_MUX],
780 .num_parents = 2,
781 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
782 }
783 },
784 [VC3_DIV4_MUX] = {
785 .data = &(struct vc3_clk_data) {
786 .offs = VC3_OUTPUT_CTR,
787 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
788 },
789 .hw.init = &(struct clk_init_data) {
790 .name = "div4_mux",
791 .ops = &vc3_div_mux_ops,
792 .parent_data = div_mux_parent_data[VC3_DIV4_MUX],
793 .num_parents = 2,
794 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
795 }
796 }
797 };
798
799 static struct vc3_hw_data clk_div[] = {
800 [VC3_DIV1] = {
801 .data = &(struct vc3_div_data) {
802 .offs = VC3_OUT_DIV1_DIV2_CTRL,
803 .table = div1_divs,
804 .shift = 4,
805 .width = 4,
806 .flags = CLK_DIVIDER_READ_ONLY
807 },
808 .hw.init = &(struct clk_init_data) {
809 .name = "div1",
810 .ops = &vc3_div_ops,
811 .parent_hws = (const struct clk_hw *[]) {
812 &clk_div_mux[VC3_DIV1_MUX].hw
813 },
814 .num_parents = 1,
815 .flags = CLK_SET_RATE_PARENT
816 }
817 },
818 [VC3_DIV2] = {
819 .data = &(struct vc3_div_data) {
820 .offs = VC3_OUT_DIV1_DIV2_CTRL,
821 .table = div245_divs,
822 .shift = 0,
823 .width = 4,
824 .flags = CLK_DIVIDER_READ_ONLY
825 },
826 .hw.init = &(struct clk_init_data) {
827 .name = "div2",
828 .ops = &vc3_div_ops,
829 .parent_hws = (const struct clk_hw *[]) {
830 &clk_pll[VC3_PLL1].hw
831 },
832 .num_parents = 1,
833 .flags = CLK_SET_RATE_PARENT
834 }
835 },
836 [VC3_DIV3] = {
837 .data = &(struct vc3_div_data) {
838 .offs = VC3_OUT_DIV3_DIV4_CTRL,
839 .table = div3_divs,
840 .shift = 4,
841 .width = 4,
842 .flags = CLK_DIVIDER_READ_ONLY
843 },
844 .hw.init = &(struct clk_init_data) {
845 .name = "div3",
846 .ops = &vc3_div_ops,
847 .parent_hws = (const struct clk_hw *[]) {
848 &clk_div_mux[VC3_DIV3_MUX].hw
849 },
850 .num_parents = 1,
851 .flags = CLK_SET_RATE_PARENT
852 }
853 },
854 [VC3_DIV4] = {
855 .data = &(struct vc3_div_data) {
856 .offs = VC3_OUT_DIV3_DIV4_CTRL,
857 .table = div245_divs,
858 .shift = 0,
859 .width = 4,
860 .flags = CLK_DIVIDER_READ_ONLY
861 },
862 .hw.init = &(struct clk_init_data) {
863 .name = "div4",
864 .ops = &vc3_div_ops,
865 .parent_hws = (const struct clk_hw *[]) {
866 &clk_div_mux[VC3_DIV4_MUX].hw
867 },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT
870 }
871 },
872 [VC3_DIV5] = {
873 .data = &(struct vc3_div_data) {
874 .offs = VC3_PLL1_CTRL_OUTDIV5,
875 .table = div245_divs,
876 .shift = 0,
877 .width = 4,
878 .flags = CLK_DIVIDER_READ_ONLY
879 },
880 .hw.init = &(struct clk_init_data) {
881 .name = "div5",
882 .ops = &vc3_div_ops,
883 .parent_hws = (const struct clk_hw *[]) {
884 &clk_pll[VC3_PLL3].hw
885 },
886 .num_parents = 1,
887 .flags = CLK_SET_RATE_PARENT
888 }
889 }
890 };
891
892 static struct vc3_hw_data clk_mux[] = {
893 [VC3_SE1_MUX] = {
894 .data = &(struct vc3_clk_data) {
895 .offs = VC3_SE1_DIV4_CTRL,
896 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
897 },
898 .hw.init = &(struct clk_init_data) {
899 .name = "se1_mux",
900 .ops = &vc3_clk_mux_ops,
901 .parent_hws = (const struct clk_hw *[]) {
902 &clk_div[VC3_DIV5].hw,
903 &clk_div[VC3_DIV4].hw
904 },
905 .num_parents = 2,
906 .flags = CLK_SET_RATE_PARENT
907 }
908 },
909 [VC3_SE2_MUX] = {
910 .data = &(struct vc3_clk_data) {
911 .offs = VC3_SE2_CTRL_REG0,
912 },
913 .hw.init = &(struct clk_init_data) {
914 .name = "se2_mux",
915 .ops = &vc3_clk_mux_ops,
916 .parent_hws = (const struct clk_hw *[]) {
917 &clk_div[VC3_DIV5].hw,
918 &clk_div[VC3_DIV4].hw
919 },
920 .num_parents = 2,
921 .flags = CLK_SET_RATE_PARENT
922 }
923 },
924 [VC3_SE3_MUX] = {
925 .data = &(struct vc3_clk_data) {
926 .offs = VC3_SE3_DIFF1_CTRL_REG,
927 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
928 },
929 .hw.init = &(struct clk_init_data) {
930 .name = "se3_mux",
931 .ops = &vc3_clk_mux_ops,
932 .parent_hws = (const struct clk_hw *[]) {
933 &clk_div[VC3_DIV2].hw,
934 &clk_div[VC3_DIV4].hw
935 },
936 .num_parents = 2,
937 .flags = CLK_SET_RATE_PARENT
938 }
939 },
940 [VC3_DIFF1_MUX] = {
941 .data = &(struct vc3_clk_data) {
942 .offs = VC3_DIFF1_CTRL_REG,
943 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
944 },
945 .hw.init = &(struct clk_init_data) {
946 .name = "diff1_mux",
947 .ops = &vc3_clk_mux_ops,
948 .parent_hws = (const struct clk_hw *[]) {
949 &clk_div[VC3_DIV1].hw,
950 &clk_div[VC3_DIV3].hw
951 },
952 .num_parents = 2,
953 .flags = CLK_SET_RATE_PARENT
954 }
955 },
956 [VC3_DIFF2_MUX] = {
957 .data = &(struct vc3_clk_data) {
958 .offs = VC3_DIFF2_CTRL_REG,
959 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
960 },
961 .hw.init = &(struct clk_init_data) {
962 .name = "diff2_mux",
963 .ops = &vc3_clk_mux_ops,
964 .parent_hws = (const struct clk_hw *[]) {
965 &clk_div[VC3_DIV1].hw,
966 &clk_div[VC3_DIV3].hw
967 },
968 .num_parents = 2,
969 .flags = CLK_SET_RATE_PARENT
970 }
971 }
972 };
973
vc3_of_clk_get(struct of_phandle_args * clkspec,void * data)974 static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
975 void *data)
976 {
977 unsigned int idx = clkspec->args[0];
978 struct clk_hw **clkout_hw = data;
979
980 if (idx >= ARRAY_SIZE(clk_out)) {
981 pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np);
982 return ERR_PTR(-EINVAL);
983 }
984
985 return clkout_hw[idx];
986 }
987
vc3_probe(struct i2c_client * client)988 static int vc3_probe(struct i2c_client *client)
989 {
990 struct device *dev = &client->dev;
991 u8 settings[NUM_CONFIG_REGISTERS];
992 const struct vc3_hw_cfg *data;
993 struct regmap *regmap;
994 const char *name;
995 int ret, i;
996
997 regmap = devm_regmap_init_i2c(client, &vc3_regmap_config);
998 if (IS_ERR(regmap))
999 return dev_err_probe(dev, PTR_ERR(regmap),
1000 "failed to allocate register map\n");
1001
1002 ret = of_property_read_u8_array(dev->of_node, "renesas,settings",
1003 settings, ARRAY_SIZE(settings));
1004 if (!ret) {
1005 /*
1006 * A raw settings array was specified in the DT. Write the
1007 * settings to the device immediately.
1008 */
1009 for (i = 0; i < NUM_CONFIG_REGISTERS; i++) {
1010 ret = regmap_write(regmap, i, settings[i]);
1011 if (ret) {
1012 dev_err(dev, "error writing to chip (%i)\n", ret);
1013 return ret;
1014 }
1015 }
1016 } else if (ret == -EOVERFLOW) {
1017 dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n",
1018 ARRAY_SIZE(settings));
1019 return ret;
1020 }
1021
1022 /* Register pfd muxes */
1023 for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) {
1024 clk_pfd_mux[i].regmap = regmap;
1025 ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw);
1026 if (ret)
1027 return dev_err_probe(dev, ret, "%s failed\n",
1028 clk_pfd_mux[i].hw.init->name);
1029 }
1030
1031 /* Register pfd's */
1032 for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) {
1033 clk_pfd[i].regmap = regmap;
1034 ret = devm_clk_hw_register(dev, &clk_pfd[i].hw);
1035 if (ret)
1036 return dev_err_probe(dev, ret, "%s failed\n",
1037 clk_pfd[i].hw.init->name);
1038 }
1039
1040 data = i2c_get_match_data(client);
1041
1042 /* Register pll's */
1043 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
1044 clk_pll[i].regmap = regmap;
1045 if (i == VC3_PLL2) {
1046 struct vc3_pll_data *pll_data = clk_pll[i].data;
1047
1048 pll_data->vco = data->pll2_vco;
1049 }
1050 ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
1051 if (ret)
1052 return dev_err_probe(dev, ret, "%s failed\n",
1053 clk_pll[i].hw.init->name);
1054 }
1055
1056 /* Register divider muxes */
1057 for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) {
1058 clk_div_mux[i].regmap = regmap;
1059 ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw);
1060 if (ret)
1061 return dev_err_probe(dev, ret, "%s failed\n",
1062 clk_div_mux[i].hw.init->name);
1063 }
1064
1065 /* Register dividers */
1066 for (i = 0; i < ARRAY_SIZE(clk_div); i++) {
1067 clk_div[i].regmap = regmap;
1068 ret = devm_clk_hw_register(dev, &clk_div[i].hw);
1069 if (ret)
1070 return dev_err_probe(dev, ret, "%s failed\n",
1071 clk_div[i].hw.init->name);
1072 }
1073
1074 /* Register clk muxes */
1075 for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
1076 clk_mux[i].regmap = regmap;
1077 if (i == VC3_SE2_MUX) {
1078 struct vc3_clk_data *clk_data = clk_mux[i].data;
1079
1080 clk_data->bitmsk = data->se2_clk_sel_msk;
1081 }
1082 ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
1083 if (ret)
1084 return dev_err_probe(dev, ret, "%s failed\n",
1085 clk_mux[i].hw.init->name);
1086 }
1087
1088 /* Register clk outputs */
1089 for (i = 0; i < ARRAY_SIZE(clk_out); i++) {
1090 switch (i) {
1091 case VC3_DIFF2:
1092 name = "diff2";
1093 break;
1094 case VC3_DIFF1:
1095 name = "diff1";
1096 break;
1097 case VC3_SE3:
1098 name = "se3";
1099 break;
1100 case VC3_SE2:
1101 name = "se2";
1102 break;
1103 case VC3_SE1:
1104 name = "se1";
1105 break;
1106 case VC3_REF:
1107 name = "ref";
1108 break;
1109 default:
1110 return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i);
1111 }
1112
1113 if (i == VC3_REF)
1114 clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev,
1115 name, 0, CLK_SET_RATE_PARENT, 1, 1);
1116 else
1117 clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev,
1118 name, &clk_mux[i - 1].hw, CLK_SET_RATE_PARENT, 1, 1);
1119
1120 if (IS_ERR(clk_out[i]))
1121 return PTR_ERR(clk_out[i]);
1122 }
1123
1124 ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out);
1125 if (ret)
1126 return dev_err_probe(dev, ret, "unable to add clk provider\n");
1127
1128 return ret;
1129 }
1130
1131 static const struct vc3_hw_cfg vc3_5p = {
1132 .pll2_vco = { .min = 400000000UL, .max = 1200000000UL },
1133 .se2_clk_sel_msk = BIT(6),
1134 };
1135
1136 static const struct vc3_hw_cfg vc3_5l = {
1137 .pll2_vco = { .min = 30000000UL, .max = 130000000UL },
1138 .se2_clk_sel_msk = BIT(0),
1139 };
1140
1141 static const struct of_device_id dev_ids[] = {
1142 { .compatible = "renesas,5p35023", .data = &vc3_5p },
1143 { .compatible = "renesas,5l35023", .data = &vc3_5l },
1144 { /* Sentinel */ }
1145 };
1146 MODULE_DEVICE_TABLE(of, dev_ids);
1147
1148 static struct i2c_driver vc3_driver = {
1149 .driver = {
1150 .name = "vc3",
1151 .of_match_table = of_match_ptr(dev_ids),
1152 },
1153 .probe = vc3_probe,
1154 };
1155 module_i2c_driver(vc3_driver);
1156
1157 MODULE_AUTHOR("Biju Das <[email protected]>");
1158 MODULE_DESCRIPTION("Renesas VersaClock 3 driver");
1159 MODULE_LICENSE("GPL");
1160