1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2024 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Samsung Exynos Mailbox Controller
9
10maintainers:
11  - Tudor Ambarus <[email protected]>
12
13description:
14  The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
15  bits for hardware interrupt generation and a shared register for passing
16  mailbox messages. When the controller is used by the ACPM interface
17  the shared register is ignored and the mailbox controller acts as a doorbell.
18  The controller just raises the interrupt to the firmware after the
19  ACPM interface has written the message to SRAM.
20
21properties:
22  compatible:
23    const: google,gs101-mbox
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    maxItems: 1
30
31  clock-names:
32    items:
33      - const: pclk
34
35  interrupts:
36    description: IRQ line for the RX mailbox.
37    maxItems: 1
38
39  '#mbox-cells':
40    const: 0
41
42required:
43  - compatible
44  - reg
45  - clocks
46  - clock-names
47  - interrupts
48  - '#mbox-cells'
49
50additionalProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55    #include <dt-bindings/clock/google,gs101.h>
56
57    soc {
58        #address-cells = <1>;
59        #size-cells = <1>;
60
61        ap2apm_mailbox: mailbox@17610000 {
62            compatible = "google,gs101-mbox";
63            reg = <0x17610000 0x1000>;
64            clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
65            clock-names = "pclk";
66            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
67            #mbox-cells = <0>;
68        };
69    };
70