1 //! [`Zeroize`] impls for ARM64 SIMD registers.
2 //!
3 //! Gated behind the `aarch64` feature: MSRV 1.59
4 //! (the overall crate is MSRV 1.51)
5 
6 use crate::{atomic_fence, volatile_write, Zeroize};
7 
8 use core::arch::aarch64::*;
9 
10 macro_rules! impl_zeroize_for_simd_register {
11     ($(($type:ty, $vdupq:ident)),+) => {
12         $(
13             #[cfg_attr(docsrs, doc(cfg(target_arch = "aarch64")))]
14             #[cfg_attr(docsrs, doc(cfg(target_feature = "neon")))]
15             impl Zeroize for $type {
16                 fn zeroize(&mut self) {
17                     volatile_write(self, unsafe { $vdupq(0) });
18                     atomic_fence();
19                 }
20             }
21         )+
22     };
23 }
24 
25 // TODO(tarcieri): other NEON register types?
26 impl_zeroize_for_simd_register! {
27     (uint8x8_t, vdup_n_u8),
28     (uint8x16_t, vdupq_n_u8),
29     (uint16x4_t, vdup_n_u16),
30     (uint16x8_t, vdupq_n_u16),
31     (uint32x2_t, vdup_n_u32),
32     (uint32x4_t, vdupq_n_u32),
33     (uint64x1_t, vdup_n_u64),
34     (uint64x2_t, vdupq_n_u64)
35 }
36