1 /* 2 * Copyright © 2020 Valve Corporation 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 #include "helpers.h" 7 #include <stdarg.h> 8 9 using namespace aco; 10 11 BEGIN_TEST(validate.sdwa.allow) 12 for (unsigned i = GFX8; i <= GFX10; i++) { 13 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 14 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 15 continue; 16 //>> Validation results: 17 //! Validation passed 18 19 SDWA_instruction* sdwa = 20 &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa(); 21 sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true; 22 23 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]); 24 25 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa(); 26 sdwa->sel[0] = SubdwordSel::sbyte2; 27 sdwa->sel[1] = SubdwordSel::uword1; 28 29 finish_validator_test(); 30 } 31 END_TEST 32 33 BEGIN_TEST(validate.sdwa.support) 34 for (unsigned i = GFX7; i <= GFX11; i++) { 35 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 36 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 37 continue; 38 //>> Validation results: 39 40 //~gfx(7|11)! SDWA is GFX8 to GFX10.3 only: v1: %t0 = v_mul_f32 %a, %b dst_sel:dword src0_sel:dword src1_sel:dword 41 //~gfx(7|11)! Validation failed 42 //~gfx([89]|10)! Validation passed 43 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 44 45 finish_validator_test(); 46 } 47 END_TEST 48 49 BEGIN_TEST(validate.sdwa.operands) 50 for (unsigned i = GFX8; i <= GFX10; i++) { 51 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 52 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 53 continue; 54 //>> Validation results: 55 56 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %sgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 57 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %vgpr0, %sgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 58 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], inputs[1]); 59 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[3]); 60 61 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 4, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 62 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 %vgpr0, 4 dst_sel:dword src0_sel:dword src1_sel:dword 63 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]); 64 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u)); 65 66 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 0x1234, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 67 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 68 //! Wrong source position for Literal argument: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 69 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]); 70 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u)); 71 72 //! Validation failed 73 74 finish_validator_test(); 75 } 76 END_TEST 77 78 BEGIN_TEST(validate.sdwa.vopc) 79 for (unsigned i = GFX8; i <= GFX10; i++) { 80 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 81 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 82 continue; 83 //>> Validation results: 84 85 bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]); 86 87 //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword 88 bld.vopc_sdwa(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), inputs[0], inputs[1]); 89 90 //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword 91 bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]) 92 ->sdwa() 93 .clamp = true; 94 95 //! Validation failed 96 97 finish_validator_test(); 98 } 99 END_TEST 100 101 BEGIN_TEST(validate.sdwa.omod) 102 for (unsigned i = GFX8; i <= GFX10; i++) { 103 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 104 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 105 continue; 106 //>> Validation results: 107 108 //~gfx8! SDWA omod only supported on GFX9+: v1: %_ = v_mul_f32 %vgpr0, %vgpr1 *2 dst_sel:dword src0_sel:dword src1_sel:dword 109 //~gfx8! Validation failed 110 //~gfx(9|10)! Validation passed 111 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa().omod = 1; 112 113 finish_validator_test(); 114 } 115 END_TEST 116 117 BEGIN_TEST(validate.sdwa.vcc) 118 for (unsigned i = GFX8; i <= GFX10; i++) { 119 //>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm 120 if (!setup_cs("v1 v1 s2", (amd_gfx_level)i)) 121 continue; 122 //>> Validation results: 123 124 //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword 125 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], inputs[2]); 126 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], 127 bld.vcc(inputs[2])); 128 129 //! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 130 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm), inputs[0], inputs[1]); 131 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], 132 inputs[1]); 133 134 //! Validation failed 135 136 finish_validator_test(); 137 } 138 END_TEST 139 140 BEGIN_TEST(optimize.sdwa.extract) 141 for (unsigned i = GFX7; i <= GFX10; i++) { 142 for (unsigned is_signed = 0; is_signed <= 1; is_signed++) { 143 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 144 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i, CHIP_UNKNOWN, 145 is_signed ? "_signed" : "_unsigned")) 146 continue; 147 148 //; def standard_test(index, sel): 149 //; res = 'v1: %%res%s = v_mul_f32 %%a, %%b dst_sel:dword src0_sel:dword src1_sel:%c%s\n' % (index, 's' if variant.endswith('_signed') else 'u', sel) 150 //; res += 'p_unit_test %s, %%res%s' % (index, index) 151 //; return res 152 //; funcs['standard_test'] = lambda a: standard_test(*(v for v in a.split(','))) 153 154 aco_opcode ext = aco_opcode::p_extract; 155 aco_opcode ins = aco_opcode::p_insert; 156 157 { 158 //~gfx[^7].*! @standard_test(0,byte0) 159 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 160 Operand::c32(8u), Operand::c32(is_signed)); 161 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte0_b)); 162 163 //~gfx[^7].*! @standard_test(1,byte1) 164 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 165 Operand::c32(8u), Operand::c32(is_signed)); 166 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte1_b)); 167 168 //~gfx[^7].*! @standard_test(2,byte2) 169 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), 170 Operand::c32(8u), Operand::c32(is_signed)); 171 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte2_b)); 172 173 //~gfx[^7].*! @standard_test(3,byte3) 174 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), 175 Operand::c32(8u), Operand::c32(is_signed)); 176 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte3_b)); 177 178 //~gfx[^7].*! @standard_test(4,word0) 179 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 180 Operand::c32(16u), Operand::c32(is_signed)); 181 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word0_b)); 182 183 //~gfx[^7].*! @standard_test(5,word1) 184 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 185 Operand::c32(16u), Operand::c32(is_signed)); 186 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word1_b)); 187 188 //~gfx[^7]_unsigned! @standard_test(6,byte0) 189 Temp bfi_byte0_b = 190 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u)); 191 writeout(6, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte0_b)); 192 193 //~gfx[^7]_unsigned! @standard_test(7,word0) 194 Temp bfi_word0_b = 195 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u)); 196 writeout(7, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_word0_b)); 197 } 198 199 //>> p_unit_test 63 200 writeout(63); 201 202 { 203 //! v1: %tmp8 = p_insert %b, 1, 8 204 //! v1: %res8 = v_mul_f32 %a, %tmp8 205 //! p_unit_test 8, %res8 206 Temp bfi_byte1_b = 207 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u)); 208 writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte1_b)); 209 210 /* v_cvt_f32_ubyte[0-3] can be used instead of v_cvt_f32_u32+sdwa */ 211 //~gfx7_signed! v1: %bfe_byte0_b = p_extract %b, 0, 8, 1 212 //~gfx7_signed! v1: %res9 = v_cvt_f32_u32 %bfe_byte0_b 213 //~gfx[^7]+_signed! v1: %res9 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte0 214 //~gfx\d+_unsigned! v1: %res9 = v_cvt_f32_ubyte0 %b 215 //! p_unit_test 9, %res9 216 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 217 Operand::c32(8u), Operand::c32(is_signed)); 218 writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b)); 219 220 //~gfx7_signed! v1: %bfe_byte1_b = p_extract %b, 1, 8, 1 221 //~gfx7_signed! v1: %res10 = v_cvt_f32_u32 %bfe_byte1_b 222 //~gfx[^7]+_signed! v1: %res10 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte1 223 //~gfx\d+_unsigned! v1: %res10 = v_cvt_f32_ubyte1 %b 224 //! p_unit_test 10, %res10 225 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 226 Operand::c32(8u), Operand::c32(is_signed)); 227 writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b)); 228 229 //~gfx7_signed! v1: %bfe_byte2_b = p_extract %b, 2, 8, 1 230 //~gfx7_signed! v1: %res11 = v_cvt_f32_u32 %bfe_byte2_b 231 //~gfx[^7]+_signed! v1: %res11 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte2 232 //~gfx\d+_unsigned! v1: %res11 = v_cvt_f32_ubyte2 %b 233 //! p_unit_test 11, %res11 234 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), 235 Operand::c32(8u), Operand::c32(is_signed)); 236 writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b)); 237 238 //~gfx7_signed! v1: %bfe_byte3_b = p_extract %b, 3, 8, 1 239 //~gfx7_signed! v1: %res12 = v_cvt_f32_u32 %bfe_byte3_b 240 //~gfx[^7]+_signed! v1: %res12 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte3 241 //~gfx\d+_unsigned! v1: %res12 = v_cvt_f32_ubyte3 %b 242 //! p_unit_test 12, %res12 243 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), 244 Operand::c32(8u), Operand::c32(is_signed)); 245 writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b)); 246 247 /* VOP3-only instructions can't use SDWA but they can use opsel on GFX9+ instead */ 248 //~gfx(9|10).*! v1: %res13 = v_add_i16 %a, %b 249 //~gfx(9|10).*! p_unit_test 13, %res13 250 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 251 Operand::c32(16u), Operand::c32(is_signed)); 252 writeout(13, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word0_b)); 253 254 //~gfx(9|10).*! v1: %res14 = v_add_i16 %a, hi(%b) 255 //~gfx(9|10).*! p_unit_test 14, %res14 256 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 257 Operand::c32(16u), Operand::c32(is_signed)); 258 writeout(14, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word1_b)); 259 } 260 261 finish_opt_test(); 262 } 263 } 264 END_TEST 265 266 BEGIN_TEST(optimize.sdwa.extract_modifiers) 267 for (unsigned i = GFX8; i <= GFX10; i++) { 268 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 269 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 270 continue; 271 272 aco_opcode ext = aco_opcode::p_extract; 273 274 //! v1: %res0 = v_mul_f32 %a, -%b dst_sel:dword src0_sel:dword src1_sel:ubyte0 275 //! p_unit_test 0, %res0 276 Temp byte0 = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 277 Operand::zero()); 278 Temp neg_byte0 = fneg(byte0); 279 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_byte0)); 280 281 //! v1: %neg = v_mul_f32 -1.0, %b 282 //! v1: %res1 = v_mul_f32 %a, %neg dst_sel:dword src0_sel:dword src1_sel:ubyte0 283 //! p_unit_test 1, %res1 284 Temp neg = fneg(inputs[1]); 285 Temp byte0_neg = 286 bld.pseudo(ext, bld.def(v1), neg, Operand::zero(), Operand::c32(8u), Operand::zero()); 287 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg)); 288 289 //! v1: %res2 = v_mul_f32 %a, |%b| dst_sel:dword src0_sel:dword src1_sel:ubyte0 290 //! p_unit_test 2, %res2 291 Temp abs_byte0 = fabs(byte0); 292 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], abs_byte0)); 293 294 //! v1: %abs = v_mul_f32 1.0, |%b| 295 //! v1: %res3 = v_mul_f32 %a, %abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 296 //! p_unit_test 3, %res3 297 Temp abs = fabs(inputs[1]); 298 Temp byte0_abs = 299 bld.pseudo(ext, bld.def(v1), abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 300 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_abs)); 301 302 //! v1: %res4 = v_mul_f32 %1, -|%2| dst_sel:dword src0_sel:dword src1_sel:ubyte0 303 //! p_unit_test 4, %res4 304 Temp neg_abs_byte0 = fneg(abs_byte0); 305 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_abs_byte0)); 306 307 //! v1: %neg_abs = v_mul_f32 -1.0, |%b| 308 //! v1: %res5 = v_mul_f32 %a, %neg_abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 309 //! p_unit_test 5, %res5 310 Temp neg_abs = fneg(abs); 311 Temp byte0_neg_abs = 312 bld.pseudo(ext, bld.def(v1), neg_abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 313 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg_abs)); 314 315 finish_opt_test(); 316 } 317 END_TEST 318 319 BEGIN_TEST(optimize.sdwa.extract.sgpr) 320 for (unsigned i = GFX8; i <= GFX10; i++) { 321 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 322 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 323 continue; 324 325 aco_opcode ext = aco_opcode::p_extract; 326 327 //~gfx8! v1: %byte0_b = p_extract %b, 0, 8, 0 328 //~gfx8! v1: %res1 = v_mul_f32 %c, %byte0_b 329 //~gfx(9|10)! v1: %res1 = v_mul_f32 %c, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 330 //! p_unit_test 1, %res1 331 Temp byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 332 Operand::zero()); 333 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_b)); 334 335 //~gfx8! v1: %byte0_c = p_extract %c, 0, 8, 0 336 //~gfx8! v1: %res2 = v_mul_f32 %a, %byte0_c 337 //~gfx(9|10)! v1: %res2 = v_mul_f32 %a, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 338 //! p_unit_test 2, %res2 339 Temp byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 340 Operand::zero()); 341 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_c)); 342 343 //~gfx8! v1: %byte0_c_2 = p_extract %c, 0, 8, 0 344 //~gfx8! v1: %res3 = v_mul_f32 %c, %byte0_c_2 345 //~gfx(9|10)! v1: %res3 = v_mul_f32 %c, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 346 //! p_unit_test 3, %res3 347 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 348 Operand::zero()); 349 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_c)); 350 351 //~gfx(8|9)! v1: %byte0_c_3 = p_extract %c, 0, 8, 0 352 //~gfx(8|9)! v1: %res4 = v_mul_f32 %d, %byte0_c_3 353 //~gfx10! v1: %res4 = v_mul_f32 %d, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 354 //! p_unit_test 4, %res4 355 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 356 Operand::zero()); 357 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[3], byte0_c)); 358 359 finish_opt_test(); 360 } 361 END_TEST 362 363 BEGIN_TEST(optimize.sdwa.from_vop3) 364 for (unsigned i = GFX8; i <= GFX10; i++) { 365 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 366 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 367 continue; 368 369 //! v1: %res0 = v_mul_f32 -|%a|, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 370 //! p_unit_test 0, %res0 371 Temp byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 372 Operand::c32(8u), Operand::zero()); 373 VALU_instruction* mul = 374 &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b)->valu(); 375 mul->neg[0] = true; 376 mul->abs[0] = true; 377 writeout(0, mul->definitions[0].getTemp()); 378 379 //~gfx8! v1: %byte0_b_0 = p_extract %b, 0, 8, 0 380 //~gfx8! v1: %res1 = v_mul_f32 %a, %byte0_b_0 *4 381 //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %b *4 dst_sel:dword src0_sel:dword src1_sel:ubyte0 382 //! p_unit_test 1, %res1 383 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 384 Operand::c32(8u), Operand::zero()); 385 mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b)->valu(); 386 mul->omod = 2; 387 writeout(1, mul->definitions[0].getTemp()); 388 389 //~gfx8! v1: %byte0_b_1 = p_extract %b, 0, 8, 0 390 //~gfx8! v1: %res2 = v_mul_f32 %byte0_b_1, %c 391 //~gfx(9|10)! v1: %res2 = v_mul_f32 %b, %c dst_sel:dword src0_sel:ubyte0 src1_sel:dword 392 //! p_unit_test 2, %res2 393 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 394 Operand::c32(8u), Operand::zero()); 395 writeout(2, bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, inputs[2])); 396 397 if (i >= GFX10) { 398 //~gfx10! v1: %byte0_b_2 = p_extract %b, 0, 8, 0 399 //~gfx10! v1: %res3 = v_mul_f32 %byte0_b_2, 0x1234 400 //~gfx10! p_unit_test 3, %res3 401 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 402 Operand::c32(8u), Operand::zero()); 403 writeout(3, 404 bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, Operand::c32(0x1234u))); 405 } 406 407 finish_opt_test(); 408 } 409 END_TEST 410 411 BEGIN_TEST(optimize.sdwa.insert) 412 for (unsigned i = GFX7; i <= GFX10; i++) { 413 //>> v1: %a, v1: %b = p_startpgm 414 if (!setup_cs("v1 v1", (amd_gfx_level)i)) 415 continue; 416 417 aco_opcode ext = aco_opcode::p_extract; 418 aco_opcode ins = aco_opcode::p_insert; 419 420 //~gfx[^7]! v1: %res0 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 421 //~gfx[^7]! p_unit_test 0, %res0 422 Temp val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 423 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 424 425 //~gfx[^7]! v1: %res1 = v_mul_f32 %a, %b dst_sel:ubyte1 src0_sel:dword src1_sel:dword 426 //~gfx[^7]! p_unit_test 1, %res1 427 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 428 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(8u))); 429 430 //~gfx[^7]! v1: %res2 = v_mul_f32 %a, %b dst_sel:ubyte2 src0_sel:dword src1_sel:dword 431 //~gfx[^7]! p_unit_test 2, %res2 432 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 433 writeout(2, bld.pseudo(ins, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u))); 434 435 //~gfx[^7]! v1: %res3 = v_mul_f32 %a, %b dst_sel:ubyte3 src0_sel:dword src1_sel:dword 436 //~gfx[^7]! p_unit_test 3, %res3 437 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 438 writeout(3, bld.pseudo(ins, bld.def(v1), val, Operand::c32(3u), Operand::c32(8u))); 439 440 //~gfx[^7]! v1: %res4 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 441 //~gfx[^7]! p_unit_test 4, %res4 442 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 443 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 444 445 //~gfx[^7]! v1: %res5 = v_mul_f32 %a, %b dst_sel:uword1 src0_sel:dword src1_sel:dword 446 //~gfx[^7]! p_unit_test 5, %res5 447 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 448 writeout(5, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 449 450 //~gfx[^7]! v1: %res6 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 451 //~gfx[^7]! p_unit_test 6, %res6 452 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 453 writeout( 454 6, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::zero())); 455 456 //~gfx[^7]! v1: %res7 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 457 //~gfx[^7]! p_unit_test 7, %res7 458 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 459 writeout( 460 7, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(16u), Operand::zero())); 461 462 //~gfx[^7]! v1: %tmp8 = v_mul_f32 %a, %b 463 //~gfx[^7]! v1: %res8 = p_extract %tmp8, 2, 8, 0 464 //~gfx[^7]! p_unit_test 8, %res8 465 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 466 writeout( 467 8, bld.pseudo(ext, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u), Operand::zero())); 468 469 //~gfx[^7]! v1: %tmp9 = v_mul_f32 %a, %b 470 //~gfx[^7]! v1: %res9 = p_extract %tmp9, 0, 8, 1 471 //~gfx[^7]! p_unit_test 9, %res9 472 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 473 writeout( 474 9, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::c32(1u))); 475 476 //>> p_unit_test 63 477 writeout(63); 478 479 //! v1: %res10 = v_mul_f32 %a, %b 480 //! p_unit_test 10, %res10 481 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 482 bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)); 483 writeout(10, val); 484 485 //~gfx[^7]! v1: %tmp11 = v_sub_i16 %a, %b 486 //~gfx[^7]! v1: %res11 = p_insert %tmp11, 0, 16 487 //~gfx[^7]! p_unit_test 11, %res11 488 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 489 writeout(11, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 490 491 //~gfx[^7]! v1: %tmp12 = v_sub_i16 %a, %b 492 //~gfx[^7]! v1: %res12 = p_insert %tmp12, 1, 16 493 //~gfx[^7]! p_unit_test 12, %res12 494 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 495 writeout(12, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 496 497 //~gfx[^7]! v1: %tmp13 = v_sub_i16 %a, %b 498 //~gfx[^7]! v1: %res13 = p_insert %tmp13, 0, 8 499 //~gfx[^7]! p_unit_test 13, %res13 500 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 501 writeout(13, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 502 503 finish_opt_test(); 504 } 505 END_TEST 506 507 BEGIN_TEST(optimize.sdwa.insert_modifiers) 508 for (unsigned i = GFX8; i <= GFX9; i++) { 509 //>> v1: %a = p_startpgm 510 if (!setup_cs("v1", (amd_gfx_level)i)) 511 continue; 512 513 aco_opcode ins = aco_opcode::p_insert; 514 515 //~gfx8! v1: %tmp0 = v_rcp_f32 %a *2 516 //~gfx8! v1: %res0 = p_insert %tmp0, 0, 8 517 //~gfx9! v1: %res0 = v_rcp_f32 %a *2 dst_sel:ubyte0 src0_sel:dword 518 //! p_unit_test 0, %res0 519 Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 520 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 521 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 522 523 //! v1: %res1 = v_rcp_f32 %a clamp dst_sel:ubyte0 src0_sel:dword 524 //! p_unit_test 1, %res1 525 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 526 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 527 Operand::c32(0x3f800000u)); 528 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 529 530 //! v1: %tmp2 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 531 //! v1: %res2 = v_mul_f32 %tmp2, 2.0 532 //! p_unit_test 2, %res2 533 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 534 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 535 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 536 writeout(2, val); 537 538 //! v1: %tmp3 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 539 //! v1: %res3 = v_add_f32 %tmp3, 0 clamp 540 //! p_unit_test 3, %res3 541 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 542 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 543 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 544 Operand::c32(0x3f800000u)); 545 writeout(3, val); 546 547 //~gfx8! v1: %tmp4 = v_rcp_f32 %a *2 clamp 548 //~gfx8! v1: %res4 = p_insert %tmp4, 0, 8 549 //~gfx9! v1: %res4 = v_rcp_f32 %a *2 clamp dst_sel:ubyte0 src0_sel:dword 550 //! p_unit_test 4, %res4 551 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 552 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 553 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 554 Operand::c32(0x3f800000u)); 555 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 556 557 finish_opt_test(); 558 } 559 END_TEST 560