1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import chisel3.internal.naming.chiselName 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31 32class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 33 34 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 35 clients = Seq(TLMasterParameters.v1( 36 "ptw", 37 sourceId = IdRange(0, MemReqWidth) 38 )) 39 ))) 40 41 lazy val module = new L2TLBImp(this) 42} 43 44@chiselName 45class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 46 47 val (mem, edge) = outer.node.out.head 48 49 val io = IO(new L2TLBIO) 50 val difftestIO = IO(new Bundle() { 51 val ptwResp = Output(Bool()) 52 val ptwAddr = Output(UInt(64.W)) 53 val ptwData = Output(Vec(4, UInt(64.W))) 54 }) 55 56 /* Ptw processes multiple requests 57 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 58 * miss queue itlb dtlb 59 * | | | 60 * ------arbiter------ 61 * | 62 * l1 - l2 - l3 - sp 63 * | 64 * ------------------------------------------- 65 * miss | queue | hit 66 * [][][][][][] | 67 * | | 68 * state machine accessing mem | 69 * | | 70 * ---------------arbiter--------------------- 71 * | | 72 * itlb dtlb 73 */ 74 75 difftestIO <> DontCare 76 77 val sfence = DelayN(io.sfence, 2) 78 val csr = DelayN(io.csr.tlb, 2) 79 val satp = csr.satp 80 val priv = csr.priv 81 val flush = sfence.valid || csr.satp.changed 82 83 val pmp = Module(new PMP()) 84 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 85 pmp.io.distribute_csr := io.csr.distribute_csr 86 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 87 88 val missQueue = Module(new L2TlbMissQueue) 89 val cache = Module(new PtwCache) 90 val ptw = Module(new PTW) 91 val llptw = Module(new LLPTW) 92 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 93 val arb2 = Module(new Arbiter(new Bundle { 94 val vpn = UInt(vpnLen.W) 95 val source = UInt(bSourceWidth.W) 96 }, if (l2tlbParams.enablePrefetch) 3 else 2)) 97 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwResp, 3)).io) 98 val outArbCachePort = 0 99 val outArbFsmPort = 1 100 val outArbMqPort = 2 101 102 // NOTE: when cache out but miss and ptw doesnt accept, 103 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 104 arb1.io.out.ready := arb2.io.in(1).ready 105 106 val InArbMissQueuePort = 0 107 val InArbTlbPort = 1 108 val InArbPrefetchPort = 2 109 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 110 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 111 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 112 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 113 if (l2tlbParams.enablePrefetch) { 114 val prefetch = Module(new L2TlbPrefetch()) 115 val recv = cache.io.resp 116 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 117 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 118 prefetch.io.in.valid := recv.fire() && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 119 recv.bits.prefetch) && recv.bits.isFirst 120 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 121 prefetch.io.sfence := sfence 122 prefetch.io.csr := csr 123 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 124 } 125 arb2.io.out.ready := cache.io.req.ready 126 127 val LLPTWARB_CACHE=0 128 val LLPTWARB_PTW=1 129 val llptw_arb = Module(new Arbiter(new LLPTWInBundle, 2)) 130 llptw_arb.io.in(LLPTWARB_CACHE).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.toFsm.l2Hit 131 llptw_arb.io.in(LLPTWARB_CACHE).bits.req_info := cache.io.resp.bits.req_info 132 llptw_arb.io.in(LLPTWARB_CACHE).bits.ppn := cache.io.resp.bits.toFsm.ppn 133 llptw_arb.io.in(LLPTWARB_PTW) <> ptw.io.llptw 134 llptw.io.in <> llptw_arb.io.out 135 llptw.io.sfence := sfence 136 llptw.io.csr := csr 137 138 cache.io.req.valid := arb2.io.out.valid 139 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 140 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 141 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 142 cache.io.sfence := sfence 143 cache.io.csr := csr 144 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 145 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 146 Mux(cache.io.resp.bits.toFsm.l2Hit, llptw_arb.io.in(LLPTWARB_CACHE).ready, 147 missQueue.io.in.ready || ptw.io.req.ready)) 148 149 missQueue.io.in.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 150 !cache.io.resp.bits.toFsm.l2Hit && !ptw.io.req.ready 151 missQueue.io.in.bits := cache.io.resp.bits.req_info 152 missQueue.io.sfence := sfence 153 missQueue.io.csr := csr 154 155 // NOTE: missQueue req has higher priority 156 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit 157 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 158 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 159 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 160 ptw.io.csr := csr 161 ptw.io.sfence := sfence 162 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 163 164 165 // mem req 166 def blockBytes_align(addr: UInt) = { 167 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 168 } 169 def addr_low_from_vpn(vpn: UInt) = { 170 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 171 } 172 def addr_low_from_paddr(paddr: UInt) = { 173 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 174 } 175 def from_missqueue(id: UInt) = { 176 (id =/= l2tlbParams.llptwsize.U) 177 } 178 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 179 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 180 for (i <- waiting_resp.indices) { 181 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 182 } 183 184 val llptw_out = llptw.io.out 185 val llptw_mem = llptw.io.mem 186 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 187 ptw.io.mem.mask := waiting_resp.last 188 189 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 2)) 190 mem_arb.io.in(0) <> ptw.io.mem.req 191 mem_arb.io.in(1) <> llptw_mem.req 192 mem_arb.io.out.ready := mem.a.ready && !flush 193 194 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 195 196 when (llptw.io.in.fire()) { 197 // when enq miss queue, set the req_addr_low to receive the mem resp data part 198 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 199 } 200 when (mem_arb.io.out.fire()) { 201 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 202 waiting_resp(mem_arb.io.out.bits.id) := true.B 203 } 204 // mem read 205 val memRead = edge.Get( 206 fromSource = mem_arb.io.out.bits.id, 207 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 208 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 209 lgSize = log2Up(l2tlbParams.blockBytes).U 210 )._2 211 mem.a.bits := memRead 212 mem.a.valid := mem_arb.io.out.valid && !flush 213 mem.d.ready := true.B 214 // mem -> data buffer 215 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 216 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire()) 217 val mem_resp_done = refill_helper._3 218 val mem_resp_from_mq = from_missqueue(mem.d.bits.source) 219 when (mem.d.valid) { 220 assert(mem.d.bits.source <= l2tlbParams.llptwsize.U) 221 refill_data(refill_helper._4) := mem.d.bits.data 222 } 223 // save only one pte for each id 224 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 225 val resp_pte = VecInit((0 until MemReqWidth).map(i => 226 if (i == l2tlbParams.llptwsize) {DataHoldBypass(get_part(refill_data, req_addr_low(i)), RegNext(mem_resp_done && !mem_resp_from_mq)) } 227 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 228 )) 229 230 // mem -> miss queue 231 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_mq 232 llptw_mem.resp.bits.id := mem.d.bits.source 233 // mem -> ptw 234 ptw.io.mem.req.ready := mem.a.ready 235 ptw.io.mem.resp.valid := mem_resp_done && !mem_resp_from_mq 236 ptw.io.mem.resp.bits := resp_pte.last 237 // mem -> cache 238 val refill_from_mq = RegNext(mem_resp_from_mq) 239 cache.io.refill.valid := RegNext(mem_resp_done && !flush && !flush_latch(mem.d.bits.source)) 240 cache.io.refill.bits.ptes := refill_data.asUInt 241 cache.io.refill.bits.req_info := Mux(refill_from_mq, llptw_mem.refill, ptw.io.refill.req_info) 242 cache.io.refill.bits.level := Mux(refill_from_mq, 2.U, RegEnable(ptw.io.refill.level, init = 0.U, ptw.io.mem.req.fire())) 243 cache.io.refill.bits.addr_low := RegNext(req_addr_low(mem.d.bits.source)) 244 245 // pmp 246 pmp_check(0).req <> ptw.io.pmp.req 247 ptw.io.pmp.resp <> pmp_check(0).resp 248 pmp_check(1).req <> llptw.io.pmp.req 249 llptw.io.pmp.resp <> pmp_check(1).resp 250 251 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 252 for (i <- 0 until PtwWidth) { 253 outArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 254 outArb(i).in(outArbCachePort).bits.entry := cache.io.resp.bits.toTlb 255 outArb(i).in(outArbCachePort).bits.pf := !cache.io.resp.bits.toTlb.v 256 outArb(i).in(outArbCachePort).bits.af := false.B 257 outArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 258 outArb(i).in(outArbFsmPort).bits := ptw.io.resp.bits.resp 259 outArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 260 outArb(i).in(outArbMqPort).bits := pte_to_ptwResp(resp_pte(llptw_out.bits.id), llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 261 } 262 263 // io.tlb.map(_.resp) <> outArb.map(_.out) 264 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 265 case (resp, out) => resp <> out 266 } 267 268 // sfence 269 when (flush) { 270 for (i <- 0 until MemReqWidth) { 271 when (waiting_resp(i)) { 272 flush_latch(i) := true.B 273 } 274 } 275 } 276 // mem -> control signal 277 // waiting_resp and sfence_latch will be reset when mem_resp_done 278 when (mem_resp_done) { 279 waiting_resp(mem.d.bits.source) := false.B 280 flush_latch(mem.d.bits.source) := false.B 281 } 282 283 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 284 sink.valid := source.valid && !block_signal 285 source.ready := sink.ready && !block_signal 286 sink.bits := source.bits 287 } 288 289 def get_part(data: Vec[UInt], index: UInt): UInt = { 290 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 291 inner_data(index) 292 } 293 294 def pte_to_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean) : PtwResp = { 295 val pte_in = pte.asTypeOf(new PteBundle()) 296 val ptw_resp = Wire(new PtwResp()) 297 ptw_resp.entry.ppn := pte_in.ppn 298 ptw_resp.entry.level.map(_ := 2.U) 299 ptw_resp.entry.perm.map(_ := pte_in.getPerm()) 300 ptw_resp.entry.tag := vpn 301 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 302 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && af 303 ptw_resp.entry.v := !ptw_resp.pf 304 ptw_resp.entry.prefetch := DontCare 305 ptw_resp.entry.asid := satp.asid 306 ptw_resp 307 } 308 309 def outReady(source: UInt, port: Int): Bool = { 310 MuxLookup(source, true.B, 311 (0 until PtwWidth).map(i => i.U -> outArb(i).in(port).ready)) 312 } 313 314 // debug info 315 for (i <- 0 until PtwWidth) { 316 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 317 } 318 XSDebug(p"[sfence] ${sfence}\n") 319 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 320 321 for (i <- 0 until PtwWidth) { 322 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire()) 323 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 324 } 325 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 326 for (i <- 0 until (MemReqWidth + 1)) { 327 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 328 } 329 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 330 XSPerfAccumulate("mem_count", mem.a.fire()) 331 332 // print configs 333 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MSHRSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 334 335 // time out assert 336 for (i <- 0 until MemReqWidth) { 337 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 338 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 339 } 340 341 342 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 343 generatePerfEvent() 344} 345 346class PTEHelper() extends ExtModule { 347 val clock = IO(Input(Clock())) 348 val enable = IO(Input(Bool())) 349 val satp = IO(Input(UInt(64.W))) 350 val vpn = IO(Input(UInt(64.W))) 351 val pte = IO(Output(UInt(64.W))) 352 val level = IO(Output(UInt(8.W))) 353 val pf = IO(Output(UInt(8.W))) 354} 355 356class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 357 val io = IO(new L2TLBIO) 358 359 for (i <- 0 until PtwWidth) { 360 io.tlb(i).req(0).ready := true.B 361 362 val helper = Module(new PTEHelper()) 363 helper.clock := clock 364 helper.enable := io.tlb(i).req(0).valid 365 helper.satp := io.csr.tlb.satp.ppn 366 helper.vpn := io.tlb(i).req(0).bits.vpn 367 val pte = helper.pte.asTypeOf(new PteBundle) 368 val level = helper.level 369 val pf = helper.pf 370 371 io.tlb(i).resp.valid := RegNext(io.tlb(i).req(0).valid) 372 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 373 io.tlb(i).resp.bits.entry.tag := RegNext(io.tlb(i).req(0).bits.vpn) 374 io.tlb(i).resp.bits.entry.ppn := pte.ppn 375 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 376 io.tlb(i).resp.bits.entry.level.map(_ := level) 377 io.tlb(i).resp.bits.pf := pf 378 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 379 } 380} 381 382class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 383 val useSoftPTW = coreParams.softPTW 384 val node = if (!useSoftPTW) TLIdentityNode() else null 385 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 386 if (!useSoftPTW) { 387 node := ptw.node 388 } 389 390 lazy val module = new LazyModuleImp(this) with HasPerfEvents { 391 val io = IO(new L2TLBIO) 392 val perfEvents = if (useSoftPTW) { 393 val fake_ptw = Module(new FakePTW()) 394 io <> fake_ptw.io 395 Seq() 396 } 397 else { 398 io <> ptw.module.io 399 ptw.module.getPerfEvents 400 } 401 generatePerfEvent() 402 } 403} 404