fix(L2TLB): Napot entries in LLPTW should not be compressed (#4396)

fix(LLPTW): Fix exception judgement for different virtualisation stages (#4404)

In the previous exception handling in LLPTW, both isAf and isGpf were
checked for all cases, including allStage, onlyS

fix(LLPTW): Fix exception judgement for different virtualisation stages (#4404)

In the previous exception handling in LLPTW, both isAf and isGpf were
checked for all cases, including allStage, onlyStage1, and noS2xlate.

In fact, for allStage, only isPf & isGpf needs to be checked, while for
onlyStage1 and noS2xlate, only isPf & isAf should be checked.

This commit fixes this issue.

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fix(L2TLB): fix `hptw_bypassed` wrong used in `refill_valid` (#4366)

The Reg `hptw_bypassed` is used to indicate a hptw's mem response no
need to refill PTWCache.
So add condition `from_hptw(mem.d.b

fix(L2TLB): fix `hptw_bypassed` wrong used in `refill_valid` (#4366)

The Reg `hptw_bypassed` is used to indicate a hptw's mem response no
need to refill PTWCache.
So add condition `from_hptw(mem.d.bits.source)` for `hptw_bypassed` used
in `refill_valid`,
to fix bug of Reg `hptw_bypassed` wrongly killing refill request from
another ptw.

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feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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fix(L2TLB): reset tlbCounter when flush (#4202)

fix(L2TLB): Fix stuck caused by MissQueue full (#4191)

In the previous design, we will ensure that L2 TLB will be able to
receive the request by repeater between L1 TLB and L2 TLB. Specifically,
t

fix(L2TLB): Fix stuck caused by MissQueue full (#4191)

In the previous design, we will ensure that L2 TLB will be able to
receive the request by repeater between L1 TLB and L2 TLB. Specifically,
the number of entries in L2 TLB MissQueue will be greater than or equal
to the sum of itlbRepeater entries + dtlbRepeater entries, so as long as
the repeater is able to accept, the L2 TLB will be able to handle.

However, there is always a problem with this approach: the repeater does
not know whether multiple reqs of the TLB will be on the same huge page
(e.g. a 2MB page), so it is possible that there may be multiple items on
the same huge page in a repeater at the same time. In this case, L2 TLB
will release more than one repeater entry at a time (these pages are in
a same huge page). However, the req and resp of L2 TLB are one-to-one
correspondence, although one resp has returned, the resp of other reqs
are still inside L2 TLB, which means that the outstanding requests in L2
TLB are more than valid entries in repeater. In this case, there is no
guarantee that the L2 TLB will be able to accept as long as the repeater
is able to accept.

This problem becomes more pronounced when TLB compression (sector TLB)
is added and the repeater is reconfigured, which may result in more
situations that L2 TLB releasing more than one repeater entries at one
time. After refactoring the repeater, the three dtlb repeaters do not
check for duplicates, so L2 TLB resp may release entries from multiple
repeaters at the same time. Due to these reasons, in the high pressure
access situation especially after the hypervisor extension is
implemented, the MissQueue of L2 TLB may be filled while the repeater
cannot intercept (the repeater still has empty entries), which finally
resulting in a stuck.

This commit fixes this issue. The fix is straightforward, simply add a
counter at top level of L2 TLB to ensure that the number of outstanding
requests inside L2 TLB will not exceed the number of entries in
MissQueue. In future MMU refactoring, we should assign idx to L2 TLB
requests like freelist, so that we can solve the problem of stuckness,
and at the same time let MissQueue know the order of the requests, so as
to avoid the performance bug that the new requests are sent out first,
and the old ones are sent out later.

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feat(Svnapot): support Svnapot extension (#4107)

chore(MMU): Remove timeout assertion (#3603)

With CHI enabled and CMN connected, a transaction may last over
timeoutThreshold. So this commit removes it (also since L2 Cache will
detect timeout)

fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type

fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type of exception that should occur in each resp
returned by L2 TLB, which is the type of exception that occurs for the
first time during the PTW process. Among them
pf & gpf: the two cases correspond to stage1 and stage2 respectively.
**In our previous design, the error is that onlyStage1 is also
considered to need gpf checking, but in fact, onlyStage1 shouldn't
report gpf.**
af: there are two kinds of access faults, the first one is the access
fault obtained by querying pmp before PTW accesses the memory, and the
second one is the access fault obtained by the PPN high level of page
table is not 0 after PTW accesses the memory. we call these two kinds of
access faults as pmp_af and ppn_af respectively.

For allStage case: pf, gpf, af can happen. pf precedes gpf (if pf is
reported in the first stage, it should be returned directly without
checking gpf in the second stage). For af, if it's pmp_af, this af will
be reported before actually accessing memory, and will have a higher
priority than pf or gpf (actually, if pmp_af occurs, no memory will be
accessed, and there will not be a pf or gpf at the same time). In case
of ppn_af, this af should actually be checked in pmp before being
reported before using this physical address for fetch or access.
However, since our physical address will be truncated directly on
return, we need to check the af in advance, and this af will have the
lowest priority and will be lower than pf | gpf. (i.e., pf and gpf will
not occur at the same time, pf > gpf. The two kinds of pf and pmp_af
will not occur at the same time, but may occur at the same time as
ppn_af, pmp_af > {pf or gpf} > ppn_af).

For onlyStage1: only pf or af will appear, same as above.
For onlyStage2: only gpf or af will appear, same as above.
For noS2xlate: only pf or af will appear, same as above.

* fix(L2TLB): prevent L1 PTEs with PPN AF to be refilled into
PageTableCache

L0 and L1 of PageTableCache caches 8 PTEs at once. When any of 8 PTEs
have a PPN with non-zero high bits, all 8 PTEs should not be refilled
into PageTableCache. Also, GPF refill filter is moved to vs generator.

* fix(L2TLB): block L2/L3 PTEs with PPN AF to be refilled

For onlyStage2, any PTE with non-zero high bits should not be refilled
into PageTableCache.

* fix(HPTW): incorrect priority of different kinds of AF and PF

In HTPW, there is 3 kinds of AF/PF:
- accessFault: PMP check failed when accessing THIS level PTE
- pageFault: this level PTE is not valid, such as v =0.
- ppn_af: the high bits of the PPN in this level PTE is not zero, which
means accessing NEXT level PTE will raise accessFault.

The priority of the above three is accessFault > pageFault > ppn_af.
This patch ensured this.

---------

Co-authored-by: Xu, Zefan <[email protected]>

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feat(pbmt): support PBMTE in MMU (#3521)

Co-authored-by: Xuan Hu <[email protected]>

fix(L2TLB, RVH): fix the assert bug when two same vpn reqs are sent to L2TLB and have af (#3523)

When two req having same vpn are sent to L2TLB, the first req has af
because of the first pte in VS

fix(L2TLB, RVH): fix the assert bug when two same vpn reqs are sent to L2TLB and have af (#3523)

When two req having same vpn are sent to L2TLB, the first req has af
because of the first pte in VS check high bits fail. This result doesn't
refill to page cache. And the next req has the same situation. Then the
assert will arise

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svpbmt: add simplified support (#3404)

Only the `pbmt` attribute is added and treated as MMIO when `pbmt` is NC
or IO.

---------

Co-authored-by: ngc7331 <[email protected]>

MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

MMU, RVH, fix the af refill error when refilling page cache (#3331)

LLPTW, RVH: fix the bug that llptw resp wrong stage1 when first s2xlate has gpf in LLPTW (#3343)

llptw_stage1 stores the result from page cache for the gpf from the
first s2xlate in llptw. LLPTW ha

LLPTW, RVH: fix the bug that llptw resp wrong stage1 when first s2xlate has gpf in LLPTW (#3343)

llptw_stage1 stores the result from page cache for the gpf from the
first s2xlate in llptw. LLPTW has many entries, so llptw_stage1 need to
add some entries in L2TLB.

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L2TLB, RVH: fix the bug that L2TLB resp wrong stage1 pte when gpf/gaf happens in LLPTW (#3164)

When gaf or gpf happens in the first stage2 translation in LLPTW, L2TLB
will resp. But LLPTW doesn't s

L2TLB, RVH: fix the bug that L2TLB resp wrong stage1 pte when gpf/gaf happens in LLPTW (#3164)

When gaf or gpf happens in the first stage2 translation in LLPTW, L2TLB
will resp. But LLPTW doesn't save the stage1 pte because LLPTW performs
the first stage2 translation. So this pr saves the stage1 pte
coresponding to the first stage2 translation.

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memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

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MMU: LLPTW should report PF when pte is not leaf (#3059)

When LLPTW looks for the last level of the page table (a 4KB page table), it must be a leaf node. The condition that the x w r bits of the pa

MMU: LLPTW should report PF when pte is not leaf (#3059)

When LLPTW looks for the last level of the page table (a 4KB page table), it must be a leaf node. The condition that the x w r bits of the page table cannot all be 0 needs to be satisfied. When this condition is not met, the LLPTW needs to report pf to the L1 TLB. (Although in practice the L1 TLB does a permission check as well, which does not result in an error from the MMU's overall perspective)

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Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

RVH: delete outdated comments (#2881)

L2TLB, RVH: fix a bug about the req which is sent to missqueue from cache

RVH: fix the errors after git rebase

RVH: hptw req will not be sent to missqueue, and add a arbiter for llptw to send req to hptw

RVH: fix some bugs about missqueue after llptw was connected to missqueue