1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import chisel3.internal.naming.chiselName 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 31import xiangshan.backend.fu.util.HasCSRConst 32import utility.ChiselDB 33 34class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )) 41 ))) 42 43 lazy val module = new L2TLBImp(this) 44} 45 46@chiselName 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(8)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(7)(RegNext(csr_tmp)) 83 val satp = csr_dup(0).satp 84 val priv = csr_dup(0).priv 85 val flush = sfence_dup(0).valid || satp.changed 86 87 val pmp = Module(new PMP()) 88 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 89 pmp.io.distribute_csr := io.csr.distribute_csr 90 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 91 92 val missQueue = Module(new L2TlbMissQueue) 93 val cache = Module(new PtwCache) 94 val ptw = Module(new PTW) 95 val llptw = Module(new LLPTW) 96 val blockmq = Module(new BlockHelper(3)) 97 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 98 val arb2 = Module(new Arbiter(new Bundle { 99 val vpn = UInt(vpnLen.W) 100 val source = UInt(bSourceWidth.W) 101 }, if (l2tlbParams.enablePrefetch) 4 else 3)) 102 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwResp, 3)).io) 103 val outArbCachePort = 0 104 val outArbFsmPort = 1 105 val outArbMqPort = 2 106 107 // arb2 input port 108 val InArbPTWPort = 0 109 val InArbMissQueuePort = 1 110 val InArbTlbPort = 2 111 val InArbPrefetchPort = 3 112 // NOTE: when cache out but miss and ptw doesnt accept, 113 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 114 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 115 116 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 117 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 118 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 119 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 120 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 121 122 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 123 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 124 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 125 if (l2tlbParams.enablePrefetch) { 126 val prefetch = Module(new L2TlbPrefetch()) 127 val recv = cache.io.resp 128 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 129 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 130 prefetch.io.in.valid := recv.fire() && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 131 recv.bits.prefetch) && recv.bits.isFirst 132 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 133 prefetch.io.sfence := sfence_dup(0) 134 prefetch.io.csr := csr_dup(0) 135 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 136 137 val L2TlbPrefetchTable = ChiselDB.createTable("L2TlbPrefetch_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbPrefetchDB) 138 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 139 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.vpn 140 L2TlbPrefetchTable.log(L2TlbPrefetchDB, prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 141 } 142 arb2.io.out.ready := cache.io.req.ready 143 144 145 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 146 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 147 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 148 !from_pre(cache.io.resp.bits.req_info.source) && 149 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 150 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 151 mq_arb.io.in(1) <> llptw.io.cache 152 missQueue.io.in <> mq_arb.io.out 153 missQueue.io.sfence := sfence_dup(6) 154 missQueue.io.csr := csr_dup(5) 155 156 blockmq.io.start := missQueue.io.out.fire 157 blockmq.io.enable := ptw.io.req.fire() 158 159 llptw.io.in.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed 160 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 161 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 162 llptw.io.sfence := sfence_dup(1) 163 llptw.io.csr := csr_dup(1) 164 165 cache.io.req.valid := arb2.io.out.valid 166 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 167 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 168 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 169 cache.io.req.bits.bypassed.map(_ := false.B) 170 cache.io.sfence := sfence_dup(2) 171 cache.io.csr := csr_dup(2) 172 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 173 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 174 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 175 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 176 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 177 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 178 179 // NOTE: missQueue req has higher priority 180 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 181 !cache.io.resp.bits.bypassed && 182 !cache.io.resp.bits.isFirst 183 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 184 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 185 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 186 ptw.io.sfence := sfence_dup(7) 187 ptw.io.csr := csr_dup(6) 188 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 189 190 // mem req 191 def blockBytes_align(addr: UInt) = { 192 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 193 } 194 def addr_low_from_vpn(vpn: UInt) = { 195 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 196 } 197 def addr_low_from_paddr(paddr: UInt) = { 198 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 199 } 200 def from_missqueue(id: UInt) = { 201 (id =/= l2tlbParams.llptwsize.U) 202 } 203 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 204 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 205 for (i <- waiting_resp.indices) { 206 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 207 } 208 209 val llptw_out = llptw.io.out 210 val llptw_mem = llptw.io.mem 211 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 212 ptw.io.mem.mask := waiting_resp.last 213 214 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 2)) 215 mem_arb.io.in(0) <> ptw.io.mem.req 216 mem_arb.io.in(1) <> llptw_mem.req 217 mem_arb.io.out.ready := mem.a.ready && !flush 218 219 // assert, should not send mem access at same addr for twice. 220 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 221 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 222 val last_resp_v = RegInit(false.B) 223 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR 224 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 225 when (flush) { last_resp_v := false.B } 226 XSError(last_resp_v && cache.io.refill.valid && 227 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 228 (cache.io.refill.bits.level_dup(0) === last_resp_level), 229 "l2tlb should not access mem at same addr for twice") 230 // ATTENTION: this may wronngly assert when: a ptes is l2, last part is valid, 231 // but the current part is invalid, so one more mem access happened 232 // If this happened, remove the assert. 233 234 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 235 236 when (llptw.io.in.fire()) { 237 // when enq miss queue, set the req_addr_low to receive the mem resp data part 238 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 239 } 240 when (mem_arb.io.out.fire()) { 241 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 242 waiting_resp(mem_arb.io.out.bits.id) := true.B 243 } 244 // mem read 245 val memRead = edge.Get( 246 fromSource = mem_arb.io.out.bits.id, 247 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 248 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 249 lgSize = log2Up(l2tlbParams.blockBytes).U 250 )._2 251 mem.a.bits := memRead 252 mem.a.valid := mem_arb.io.out.valid && !flush 253 mem.d.ready := true.B 254 // mem -> data buffer 255 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 256 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire()) 257 val mem_resp_done = refill_helper._3 258 val mem_resp_from_mq = from_missqueue(mem.d.bits.source) 259 when (mem.d.valid) { 260 assert(mem.d.bits.source <= l2tlbParams.llptwsize.U) 261 refill_data(refill_helper._4) := mem.d.bits.data 262 } 263 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 264 val refill_data_tmp = WireInit(refill_data) 265 refill_data_tmp(refill_helper._4) := mem.d.bits.data 266 267 // save only one pte for each id 268 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 269 val resp_pte = VecInit((0 until MemReqWidth).map(i => 270 if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && !mem_resp_from_mq) } 271 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 272 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 273 )) 274 275 // mem -> miss queue 276 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_mq 277 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 278 // mem -> ptw 279 ptw.io.mem.req.ready := mem.a.ready 280 ptw.io.mem.resp.valid := mem_resp_done && !mem_resp_from_mq 281 ptw.io.mem.resp.bits := resp_pte.last 282 // mem -> cache 283 val refill_from_mq = mem_resp_from_mq 284 val refill_level = Mux(refill_from_mq, 2.U, RegEnable(ptw.io.refill.level, init = 0.U, ptw.io.mem.req.fire())) 285 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 286 287 cache.io.refill.valid := RegNext(refill_valid, false.B) 288 cache.io.refill.bits.ptes := refill_data.asUInt 289 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_mq, llptw_mem.refill, ptw.io.refill.req_info), refill_valid)) 290 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 291 cache.io.refill.bits.levelOH(refill_level, refill_valid) 292 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 293 294 // pmp 295 pmp_check(0).req <> ptw.io.pmp.req 296 ptw.io.pmp.resp <> pmp_check(0).resp 297 pmp_check(1).req <> llptw.io.pmp.req 298 llptw.io.pmp.resp <> pmp_check(1).resp 299 300 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 301 for (i <- 0 until PtwWidth) { 302 outArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 303 outArb(i).in(outArbCachePort).bits.entry := cache.io.resp.bits.toTlb 304 outArb(i).in(outArbCachePort).bits.pf := !cache.io.resp.bits.toTlb.v 305 outArb(i).in(outArbCachePort).bits.af := false.B 306 outArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 307 outArb(i).in(outArbFsmPort).bits := ptw.io.resp.bits.resp 308 outArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 309 outArb(i).in(outArbMqPort).bits := pte_to_ptwResp(resp_pte(llptw_out.bits.id), llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 310 } 311 312 // io.tlb.map(_.resp) <> outArb.map(_.out) 313 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 314 case (resp, out) => resp <> out 315 } 316 317 // sfence 318 when (flush) { 319 for (i <- 0 until MemReqWidth) { 320 when (waiting_resp(i)) { 321 flush_latch(i) := true.B 322 } 323 } 324 } 325 // mem -> control signal 326 // waiting_resp and sfence_latch will be reset when mem_resp_done 327 when (mem_resp_done) { 328 waiting_resp(mem.d.bits.source) := false.B 329 flush_latch(mem.d.bits.source) := false.B 330 } 331 332 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 333 sink.valid := source.valid && !block_signal 334 source.ready := sink.ready && !block_signal 335 sink.bits := source.bits 336 } 337 338 def get_part(data: Vec[UInt], index: UInt): UInt = { 339 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 340 inner_data(index) 341 } 342 343 def pte_to_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean) : PtwResp = { 344 val pte_in = pte.asTypeOf(new PteBundle()) 345 val ptw_resp = Wire(new PtwResp()) 346 ptw_resp.entry.ppn := pte_in.ppn 347 ptw_resp.entry.level.map(_ := 2.U) 348 ptw_resp.entry.perm.map(_ := pte_in.getPerm()) 349 ptw_resp.entry.tag := vpn 350 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 351 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && af 352 ptw_resp.entry.v := !ptw_resp.pf 353 ptw_resp.entry.prefetch := DontCare 354 ptw_resp.entry.asid := satp.asid 355 ptw_resp 356 } 357 358 def outReady(source: UInt, port: Int): Bool = { 359 MuxLookup(source, true.B, 360 (0 until PtwWidth).map(i => i.U -> outArb(i).in(port).ready)) 361 } 362 363 // debug info 364 for (i <- 0 until PtwWidth) { 365 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 366 } 367 XSDebug(p"[sfence] ${io.sfence}\n") 368 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 369 370 for (i <- 0 until PtwWidth) { 371 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire()) 372 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 373 } 374 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 375 for (i <- 0 until (MemReqWidth + 1)) { 376 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 377 } 378 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 379 XSPerfAccumulate("mem_count", mem.a.fire()) 380 381 // print configs 382 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 383 384 // time out assert 385 for (i <- 0 until MemReqWidth) { 386 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 387 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 388 } 389 390 391 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 392 generatePerfEvent() 393 394 val L1TlbTable = ChiselDB.createTable("L1Tlb_hart" + p(XSCoreParamsKey).HartId.toString, new L1TlbDB) 395 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 396 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 397 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 398 ITlbRespDB.vpn := io.tlb(0).resp.bits.entry.tag 399 DTlbRespDB.vpn := io.tlb(1).resp.bits.entry.tag 400 L1TlbTable.log(ITlbReqDB, io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 401 L1TlbTable.log(DTlbReqDB, io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 402 L1TlbTable.log(ITlbRespDB, io.tlb(0).resp.fire, "ITlbResp", clock, reset) 403 L1TlbTable.log(DTlbRespDB, io.tlb(1).resp.fire, "DTlbResp", clock, reset) 404 405 val PageCacheTable = ChiselDB.createTable("PageCache_hart" + p(XSCoreParamsKey).HartId.toString, new PageCacheDB) 406 val PageCacheDB = Wire(new PageCacheDB) 407 PageCacheDB.vpn := cache.io.resp.bits.toTlb.tag 408 PageCacheDB.source := cache.io.resp.bits.req_info.source 409 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 410 PageCacheDB.is_first := cache.io.resp.bits.isFirst 411 PageCacheDB.prefetched := cache.io.resp.bits.toTlb.prefetch 412 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 413 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 414 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 415 PageCacheDB.hit := cache.io.resp.bits.hit 416 PageCacheTable.log(PageCacheDB, cache.io.resp.fire, "PageCache", clock, reset) 417 418 val PTWTable = ChiselDB.createTable("PTW_hart" + p(XSCoreParamsKey).HartId.toString, new PTWDB) 419 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 420 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 421 PTWReqDB.source := ptw.io.req.bits.req_info.source 422 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 423 PTWRespDB.source := ptw.io.refill.req_info.source 424 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 425 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 426 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 427 LLPTWRespDB.source := llptw.io.mem.refill.source 428 PTWTable.log(PTWReqDB, ptw.io.req.fire, "PTWReq", clock, reset) 429 PTWTable.log(PTWRespDB, ptw.io.mem.resp.fire, "PTWResp", clock, reset) 430 PTWTable.log(LLPTWReqDB, llptw.io.in.fire, "LLPTWReq", clock, reset) 431 PTWTable.log(LLPTWRespDB, llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 432 433 val L2TlbMissQueueTable = ChiselDB.createTable("L2TlbMissQueue_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbMissQueueDB) 434 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 435 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.vpn 436 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.vpn 437 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 438 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 439} 440 441/** BlockHelper, block missqueue, not to send too many req to cache 442 * Parameter: 443 * enable: enable BlockHelper, mq should not send too many reqs 444 * start: when miss queue out fire and need, block miss queue's out 445 * block: block miss queue's out 446 * latency: last missqueue out's cache access latency 447 */ 448class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 449 val io = IO(new Bundle { 450 val enable = Input(Bool()) 451 val start = Input(Bool()) 452 val block = Output(Bool()) 453 }) 454 455 val count = RegInit(0.U(log2Ceil(latency).W)) 456 val valid = RegInit(false.B) 457 val work = RegInit(true.B) 458 459 io.block := valid 460 461 when (io.start && work) { valid := true.B } 462 when (valid) { count := count + 1.U } 463 when (count === (latency.U) || io.enable) { 464 valid := false.B 465 work := io.enable 466 count := 0.U 467 } 468} 469 470class PTEHelper() extends ExtModule { 471 val clock = IO(Input(Clock())) 472 val enable = IO(Input(Bool())) 473 val satp = IO(Input(UInt(64.W))) 474 val vpn = IO(Input(UInt(64.W))) 475 val pte = IO(Output(UInt(64.W))) 476 val level = IO(Output(UInt(8.W))) 477 val pf = IO(Output(UInt(8.W))) 478} 479 480class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 481 val io = IO(new Bundle() { 482 val in = Input(gen) 483 val out = Output(gen) 484 val ptwflush = Input(flush.cloneType) 485 }) 486 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 487 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 488 out(0) := io.in 489 if (n == 1) { 490 io.out := out(0) 491 } else { 492 when (io.ptwflush) { 493 for (i <- 0 until n) { 494 t(i) := 0.U.asTypeOf(gen) 495 out(i) := 0.U.asTypeOf(gen) 496 } 497 io.out := 0.U.asTypeOf(gen) 498 } .otherwise { 499 for (i <- 1 until n) { 500 t(i-1) := out(i-1) 501 out(i) := t(i-1) 502 } 503 io.out := out(n-1) 504 } 505 } 506} 507 508object PTWDelayN { 509 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 510 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 511 delay.io.in := in 512 delay.io.ptwflush := flush 513 delay.io.out 514 } 515} 516 517class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 518 val io = IO(new L2TLBIO) 519 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 520 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 521 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 522 for (i <- 0 until PtwWidth) { 523 val helper = Module(new PTEHelper()) 524 helper.clock := clock 525 helper.satp := io.csr.tlb.satp.ppn 526 527 if (coreParams.softPTWDelay == 1) { 528 helper.enable := io.tlb(i).req(0).fire 529 helper.vpn := io.tlb(i).req(0).bits.vpn 530 } else { 531 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 532 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 533 } 534 535 val pte = helper.pte.asTypeOf(new PteBundle) 536 val level = helper.level 537 val pf = helper.pf 538 val empty = RegInit(true.B) 539 when (io.tlb(i).req(0).fire) { 540 empty := false.B 541 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 542 empty := true.B 543 } 544 545 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 546 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 547 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 548 io.tlb(i).resp.bits.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 549 io.tlb(i).resp.bits.entry.ppn := pte.ppn 550 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 551 io.tlb(i).resp.bits.entry.level.map(_ := level) 552 io.tlb(i).resp.bits.pf := pf 553 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 554 io.tlb(i).resp.bits.entry.v := !pf 555 io.tlb(i).resp.bits.entry.prefetch := DontCare 556 io.tlb(i).resp.bits.entry.asid := io.csr.tlb.satp.asid 557 } 558} 559 560class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 561 val useSoftPTW = coreParams.softPTW 562 val node = if (!useSoftPTW) TLIdentityNode() else null 563 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 564 if (!useSoftPTW) { 565 node := ptw.node 566 } 567 568 lazy val module = new LazyModuleImp(this) with HasPerfEvents { 569 val io = IO(new L2TLBIO) 570 val perfEvents = if (useSoftPTW) { 571 val fake_ptw = Module(new FakePTW()) 572 io <> fake_ptw.io 573 Seq() 574 } 575 else { 576 io <> ptw.module.io 577 ptw.module.getPerfEvents 578 } 579 generatePerfEvent() 580 } 581} 582