1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31import difftest._ 32 33class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 34 override def shouldBeInlined: Boolean = false 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )), 41 requestFields = Seq(ReqSourceField()) 42 ))) 43 44 lazy val module = new L2TLBImp(this) 45} 46 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(9)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(8)(RegNext(csr_tmp)) // TODO: add csr_modified? 83 val satp = csr_dup(0).satp 84 val vsatp = csr_dup(0).vsatp 85 val hgatp = csr_dup(0).hgatp 86 val priv = csr_dup(0).priv 87 val mPBMTE = csr_dup(0).mPBMTE 88 val hPBMTE = csr_dup(0).hPBMTE 89 val flush = sfence_dup(0).valid || satp.changed || vsatp.changed || hgatp.changed 90 91 val pmp = Module(new PMP()) 92 val pmp_check = VecInit(Seq.fill(3)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 93 pmp.io.distribute_csr := io.csr.distribute_csr 94 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 95 96 val missQueue = Module(new L2TlbMissQueue) 97 val cache = Module(new PtwCache) 98 val ptw = Module(new PTW) 99 val hptw = Module(new HPTW) 100 val llptw = Module(new LLPTW) 101 val blockmq = Module(new BlockHelper(3)) 102 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 103 val arb2 = Module(new Arbiter(new L2TlbWithHptwIdBundle, ((if (l2tlbParams.enablePrefetch) 4 else 3) + (if(HasHExtension) 1 else 0)))) 104 val hptw_req_arb = Module(new Arbiter(new Bundle { 105 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 106 val source = UInt(bSourceWidth.W) 107 val gvpn = UInt(gvpnLen.W) 108 }, 2)) 109 val hptw_resp_arb = Module(new Arbiter(new Bundle { 110 val resp = new HptwResp() 111 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 112 }, 2)) 113 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 114 val s2xlate = UInt(2.W) 115 val s1 = new PtwSectorResp () 116 val s2 = new HptwResp() 117 }, 1)).io) 118 val mergeArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 119 val s2xlate = UInt(2.W) 120 val s1 = new PtwMergeResp() 121 val s2 = new HptwResp() 122 }, 3)).io) 123 val outArbCachePort = 0 124 val outArbFsmPort = 1 125 val outArbMqPort = 2 126 127 // hptw arb input port 128 val InHptwArbPTWPort = 0 129 val InHptwArbLLPTWPort = 1 130 hptw_req_arb.io.in(InHptwArbPTWPort).valid := ptw.io.hptw.req.valid 131 hptw_req_arb.io.in(InHptwArbPTWPort).bits.gvpn := ptw.io.hptw.req.bits.gvpn 132 hptw_req_arb.io.in(InHptwArbPTWPort).bits.id := ptw.io.hptw.req.bits.id 133 hptw_req_arb.io.in(InHptwArbPTWPort).bits.source := ptw.io.hptw.req.bits.source 134 ptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbPTWPort).ready 135 136 hptw_req_arb.io.in(InHptwArbLLPTWPort).valid := llptw.io.hptw.req.valid 137 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.gvpn := llptw.io.hptw.req.bits.gvpn 138 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.id := llptw.io.hptw.req.bits.id 139 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.source := llptw.io.hptw.req.bits.source 140 llptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbLLPTWPort).ready 141 142 // arb2 input port 143 val InArbHPTWPort = 0 144 val InArbPTWPort = 1 145 val InArbMissQueuePort = 2 146 val InArbTlbPort = 3 147 val InArbPrefetchPort = 4 148 // NOTE: when cache out but miss and ptw doesnt accept, 149 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 150 151 val tlbCounter = RegInit(0.U(log2Ceil(MissQueueSize + 1).W)) 152 val reqVec = WireInit(VecInit(Seq.fill(PtwWidth)(false.B))) 153 val respVec = WireInit(VecInit(Seq.fill(PtwWidth)(false.B))) 154 155 for (i <- 0 until PtwWidth) { 156 when (io.tlb(i).req(0).fire) { 157 reqVec(i) := true.B 158 } 159 when (io.tlb(i).resp.fire) { 160 respVec(i) := true.B 161 } 162 } 163 164 tlbCounter := tlbCounter + PopCount(reqVec) - PopCount(respVec) 165 XSError(!(tlbCounter >= 0.U && tlbCounter <= MissQueueSize.U), s"l2tlb full!") 166 167 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 168 arb2.io.in(InArbPTWPort).bits.req_info := ptw.io.llptw.bits.req_info 169 arb2.io.in(InArbPTWPort).bits.isHptwReq := false.B 170 arb2.io.in(InArbPTWPort).bits.isLLptw := false.B 171 arb2.io.in(InArbPTWPort).bits.hptwId := DontCare 172 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 173 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), Mux(missQueue.io.out.bits.isLLptw, !llptw.io.in.ready, !ptw.io.req.ready)) 174 175 arb2.io.in(InArbTlbPort).valid := arb1.io.out.fire 176 arb2.io.in(InArbTlbPort).bits.req_info.vpn := arb1.io.out.bits.vpn 177 arb2.io.in(InArbTlbPort).bits.req_info.s2xlate := arb1.io.out.bits.s2xlate 178 arb2.io.in(InArbTlbPort).bits.req_info.source := arb1.io.chosen 179 arb2.io.in(InArbTlbPort).bits.isHptwReq := false.B 180 arb2.io.in(InArbTlbPort).bits.isLLptw := false.B 181 arb2.io.in(InArbTlbPort).bits.hptwId := DontCare 182 // 1. arb1 and arb2 are both comb logic, so ready can work just the same cycle 183 // 2. arb1 can send one req at most in a cycle, so do not need to write 184 // "tlbCounter <= (MissQueueSize - 2).U" 185 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready && tlbCounter < MissQueueSize.U 186 187 arb2.io.in(InArbHPTWPort).valid := hptw_req_arb.io.out.valid 188 arb2.io.in(InArbHPTWPort).bits.req_info.vpn := hptw_req_arb.io.out.bits.gvpn 189 arb2.io.in(InArbHPTWPort).bits.req_info.s2xlate := onlyStage2 190 arb2.io.in(InArbHPTWPort).bits.req_info.source := hptw_req_arb.io.out.bits.source 191 arb2.io.in(InArbHPTWPort).bits.isHptwReq := true.B 192 arb2.io.in(InArbHPTWPort).bits.isLLptw := false.B 193 arb2.io.in(InArbHPTWPort).bits.hptwId := hptw_req_arb.io.out.bits.id 194 hptw_req_arb.io.out.ready := arb2.io.in(InArbHPTWPort).ready 195 val hartId = p(XSCoreParamsKey).HartId 196 if (l2tlbParams.enablePrefetch) { 197 val prefetch = Module(new L2TlbPrefetch()) 198 val recv = cache.io.resp 199 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 200 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 201 prefetch.io.in.valid := recv.fire && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 202 recv.bits.prefetch) && recv.bits.isFirst 203 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 204 prefetch.io.sfence := sfence_dup(0) 205 prefetch.io.csr := csr_dup(0) 206 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 207 208 val isWriteL2TlbPrefetchTable = Constantin.createRecord(s"isWriteL2TlbPrefetchTable$hartId") 209 val L2TlbPrefetchTable = ChiselDB.createTable(s"L2TlbPrefetch_hart$hartId", new L2TlbPrefetchDB) 210 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 211 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.req_info.vpn 212 L2TlbPrefetchTable.log(L2TlbPrefetchDB, isWriteL2TlbPrefetchTable.orR && prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 213 } 214 arb2.io.out.ready := cache.io.req.ready 215 216 217 val mq_arb = Module(new Arbiter(new L2TlbWithHptwIdBundle, 2)) 218 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 219 !from_pre(cache.io.resp.bits.req_info.source) && !cache.io.resp.bits.isHptwReq && // hptw reqs are not sent to missqueue 220 (cache.io.resp.bits.bypassed || ( 221 ((!cache.io.resp.bits.toFsm.l1Hit || cache.io.resp.bits.toFsm.stage1Hit) && !cache.io.resp.bits.isHptwReq && (cache.io.resp.bits.isFirst || !ptw.io.req.ready)) // send to ptw, is first or ptw is busy; 222 || (cache.io.resp.bits.toFsm.l1Hit && !llptw.io.in.ready) // send to llptw, llptw is full 223 )) 224 225 mq_arb.io.in(0).bits.req_info := cache.io.resp.bits.req_info 226 mq_arb.io.in(0).bits.isHptwReq := false.B 227 mq_arb.io.in(0).bits.hptwId := DontCare 228 mq_arb.io.in(0).bits.isLLptw := cache.io.resp.bits.toFsm.l1Hit 229 mq_arb.io.in(1).bits.req_info := llptw.io.cache.bits 230 mq_arb.io.in(1).bits.isHptwReq := false.B 231 mq_arb.io.in(1).bits.hptwId := DontCare 232 mq_arb.io.in(1).bits.isLLptw := false.B 233 mq_arb.io.in(1).valid := llptw.io.cache.valid 234 llptw.io.cache.ready := mq_arb.io.in(1).ready 235 missQueue.io.in <> mq_arb.io.out 236 missQueue.io.sfence := sfence_dup(6) 237 missQueue.io.csr := csr_dup(5) 238 239 blockmq.io.start := missQueue.io.out.fire 240 blockmq.io.enable := ptw.io.req.fire 241 242 llptw.io.in.valid := cache.io.resp.valid && 243 !cache.io.resp.bits.hit && 244 cache.io.resp.bits.toFsm.l1Hit && 245 !cache.io.resp.bits.bypassed && 246 !cache.io.resp.bits.isHptwReq 247 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 248 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 249 llptw.io.sfence := sfence_dup(1) 250 llptw.io.csr := csr_dup(1) 251 val llptw_stage1 = Reg(Vec(l2tlbParams.llptwsize, new PtwMergeResp())) 252 when(llptw.io.in.fire){ 253 llptw_stage1(llptw.io.mem.enq_ptr) := cache.io.resp.bits.stage1 254 } 255 256 cache.io.req.valid := arb2.io.out.fire 257 cache.io.req.bits.req_info := arb2.io.out.bits.req_info 258 cache.io.req.bits.isFirst := (arb2.io.chosen =/= InArbMissQueuePort.U && !arb2.io.out.bits.isHptwReq) 259 cache.io.req.bits.isHptwReq := arb2.io.out.bits.isHptwReq 260 cache.io.req.bits.hptwId := arb2.io.out.bits.hptwId 261 cache.io.req.bits.bypassed.map(_ := false.B) 262 cache.io.sfence := sfence_dup(2) 263 cache.io.csr := csr_dup(2) 264 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 265 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 266 cache.io.resp.ready := MuxCase(mq_arb.io.in(0).ready || ptw.io.req.ready, Seq( 267 (!cache.io.resp.bits.hit && cache.io.resp.bits.isHptwReq) -> hptw.io.req.ready, 268 (cache.io.resp.bits.hit && cache.io.resp.bits.isHptwReq) -> hptw_resp_arb.io.in(HptwRespArbCachePort).ready, 269 cache.io.resp.bits.hit -> outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 270 (cache.io.resp.bits.toFsm.l1Hit && !cache.io.resp.bits.bypassed && llptw.io.in.ready) -> llptw.io.in.ready, 271 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst) -> mq_arb.io.in(0).ready 272 )) 273 274 // NOTE: missQueue req has higher priority 275 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l1Hit && 276 !cache.io.resp.bits.bypassed && 277 !cache.io.resp.bits.isFirst && 278 !cache.io.resp.bits.isHptwReq 279 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 280 if (EnableSv48) { 281 ptw.io.req.bits.l3Hit.get := cache.io.resp.bits.toFsm.l3Hit.get 282 } 283 ptw.io.req.bits.l2Hit := cache.io.resp.bits.toFsm.l2Hit 284 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 285 ptw.io.req.bits.stage1Hit := cache.io.resp.bits.toFsm.stage1Hit 286 ptw.io.req.bits.stage1 := cache.io.resp.bits.stage1 287 ptw.io.sfence := sfence_dup(7) 288 ptw.io.csr := csr_dup(6) 289 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 290 291 hptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.isHptwReq 292 hptw.io.req.bits.gvpn := cache.io.resp.bits.req_info.vpn 293 hptw.io.req.bits.id := cache.io.resp.bits.toHptw.id 294 hptw.io.req.bits.source := cache.io.resp.bits.req_info.source 295 if (EnableSv48) { 296 hptw.io.req.bits.l3Hit.get := cache.io.resp.bits.toHptw.l3Hit.get 297 } 298 hptw.io.req.bits.l2Hit := cache.io.resp.bits.toHptw.l2Hit 299 hptw.io.req.bits.l1Hit := cache.io.resp.bits.toHptw.l1Hit 300 hptw.io.req.bits.ppn := cache.io.resp.bits.toHptw.ppn 301 hptw.io.req.bits.bypassed := cache.io.resp.bits.toHptw.bypassed 302 hptw.io.sfence := sfence_dup(8) 303 hptw.io.csr := csr_dup(7) 304 // mem req 305 def blockBytes_align(addr: UInt) = { 306 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 307 } 308 def addr_low_from_vpn(vpn: UInt) = { 309 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 310 } 311 def addr_low_from_paddr(paddr: UInt) = { 312 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 313 } 314 def from_llptw(id: UInt) = { 315 id < l2tlbParams.llptwsize.U 316 } 317 def from_ptw(id: UInt) = { 318 id === l2tlbParams.llptwsize.U 319 } 320 def from_hptw(id: UInt) = { 321 id === l2tlbParams.llptwsize.U + 1.U 322 } 323 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 324 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 325 val hptw_bypassed = RegInit(false.B) 326 for (i <- waiting_resp.indices) { 327 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 328 } 329 330 val llptw_out = llptw.io.out 331 val llptw_mem = llptw.io.mem 332 llptw_mem.flush_latch := flush_latch.take(l2tlbParams.llptwsize) 333 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 334 ptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize) 335 hptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize + 1) 336 337 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 3)) 338 mem_arb.io.in(0) <> ptw.io.mem.req 339 mem_arb.io.in(1) <> llptw_mem.req 340 mem_arb.io.in(2) <> hptw.io.mem.req 341 mem_arb.io.out.ready := mem.a.ready && !flush 342 343 // // assert, should not send mem access at same addr for twice. 344 // val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 345 // val last_resp_s2xlate = RegEnable(cache.io.refill.bits.req_info_dup(0).s2xlate, cache.io.refill.valid) 346 // val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 347 // val last_resp_v = RegInit(false.B) 348 // val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR || cache.io.refill.bits.sel_pte_dup(0).asTypeOf(new PteBundle).isAf() 349 // when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 350 // when (flush) { last_resp_v := false.B } 351 // XSError(last_resp_v && cache.io.refill.valid && 352 // (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 353 // (cache.io.refill.bits.level_dup(0) === last_resp_level) && 354 // (cache.io.refill.bits.req_info_dup(0).s2xlate === last_resp_s2xlate), 355 // "l2tlb should not access mem at same addr for twice") 356 // // ATTENTION: this may wrongly assert when: a ptes is l2, last part is valid, 357 // // but the current part is invalid, so one more mem access happened 358 // // If this happened, remove the assert. 359 360 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 361 362 when (llptw.io.in.fire) { 363 // when enq miss queue, set the req_addr_low to receive the mem resp data part 364 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 365 } 366 when (mem_arb.io.out.fire) { 367 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 368 waiting_resp(mem_arb.io.out.bits.id) := true.B 369 hptw_bypassed := from_hptw(mem_arb.io.out.bits.id) && mem_arb.io.out.bits.hptw_bypassed 370 } 371 // mem read 372 val memRead = edge.Get( 373 fromSource = mem_arb.io.out.bits.id, 374 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 375 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 376 lgSize = log2Up(l2tlbParams.blockBytes).U 377 )._2 378 mem.a.bits := memRead 379 mem.a.valid := mem_arb.io.out.valid && !flush 380 mem.a.bits.user.lift(ReqSourceKey).foreach(_ := MemReqSource.PTW.id.U) 381 mem.d.ready := true.B 382 // mem -> data buffer 383 val refill_data = RegInit(VecInit.fill(blockBits / l1BusDataWidth)(0.U(l1BusDataWidth.W))) 384 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire) 385 val mem_resp_done = refill_helper._3 386 val mem_resp_from_llptw = from_llptw(mem.d.bits.source) 387 val mem_resp_from_ptw = from_ptw(mem.d.bits.source) 388 val mem_resp_from_hptw = from_hptw(mem.d.bits.source) 389 when (mem.d.valid) { 390 assert(mem.d.bits.source < MemReqWidth.U) 391 refill_data(refill_helper._4) := mem.d.bits.data 392 } 393 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 394 val refill_data_tmp = WireInit(refill_data) 395 refill_data_tmp(refill_helper._4) := mem.d.bits.data 396 397 // save only one pte for each id 398 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 399 val resp_pte = VecInit((0 until MemReqWidth).map(i => 400 if (i == l2tlbParams.llptwsize + 1) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), 0.U.asTypeOf(get_part(refill_data_tmp, req_addr_low(i))), mem_resp_done && mem_resp_from_hptw) } 401 else if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), 0.U.asTypeOf(get_part(refill_data_tmp, req_addr_low(i))), mem_resp_done && mem_resp_from_ptw) } 402 else { Mux(llptw_mem.buffer_it(i), get_part(refill_data, req_addr_low(i)), RegEnable(get_part(refill_data, req_addr_low(i)), 0.U.asTypeOf(get_part(refill_data, req_addr_low(i))), llptw_mem.buffer_it(i))) } 403 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 404 )) 405 406 // save eight ptes for each id when sector tlb 407 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 408 val resp_pte_sector = VecInit((0 until MemReqWidth).map(i => 409 if (i == l2tlbParams.llptwsize + 1) {RegEnable(refill_data_tmp, 0.U.asTypeOf(refill_data_tmp), mem_resp_done && mem_resp_from_hptw) } 410 else if (i == l2tlbParams.llptwsize) {RegEnable(refill_data_tmp, 0.U.asTypeOf(refill_data_tmp), mem_resp_done && mem_resp_from_ptw) } 411 else { Mux(llptw_mem.buffer_it(i), refill_data, RegEnable(refill_data, 0.U.asTypeOf(refill_data), llptw_mem.buffer_it(i))) } 412 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 413 )) 414 415 // mem -> llptw 416 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_llptw 417 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 418 llptw_mem.resp.bits.value := DataHoldBypass(refill_data_tmp.asUInt, mem.d.valid) 419 // mem -> ptw 420 ptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_ptw 421 ptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize) 422 // mem -> hptw 423 hptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_hptw 424 hptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize + 1) 425 // mem -> cache 426 val refill_from_llptw = mem_resp_from_llptw 427 val refill_from_ptw = mem_resp_from_ptw 428 val refill_from_hptw = mem_resp_from_hptw 429 val refill_level = Mux(refill_from_llptw, 0.U, Mux(refill_from_ptw, RegEnable(ptw.io.refill.level, 0.U, ptw.io.mem.req.fire), RegEnable(hptw.io.refill.level, 0.U, hptw.io.mem.req.fire))) 430 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) && !hptw_bypassed 431 432 cache.io.refill.valid := GatedValidRegNext(refill_valid, false.B) 433 cache.io.refill.bits.ptes := refill_data.asUInt 434 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_llptw, llptw_mem.refill, Mux(refill_from_ptw, ptw.io.refill.req_info, hptw.io.refill.req_info)), refill_valid)) 435 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 436 cache.io.refill.bits.levelOH(refill_level, refill_valid) 437 cache.io.refill.bits.sel_pte_dup.map(_ := RegEnable(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)), refill_valid)) 438 439 if (env.EnableDifftest) { 440 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W)))) 441 when (mem.a.valid) { 442 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address 443 } 444 445 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) 446 difftest.coreid := io.hartId 447 difftest.index := 2.U 448 difftest.valid := cache.io.refill.valid 449 difftest.addr := difftest_ptw_addr(RegEnable(mem.d.bits.source, mem.d.valid)) 450 difftest.data := refill_data.asTypeOf(difftest.data) 451 difftest.idtfr := DontCare 452 } 453 454 if (env.EnableDifftest) { 455 for (i <- 0 until PtwWidth) { 456 val difftest = DifftestModule(new DiffL2TLBEvent) 457 difftest.coreid := io.hartId 458 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.s1.af && !io.tlb(i).resp.bits.s2.gaf 459 difftest.index := i.U 460 difftest.vpn := Cat(io.tlb(i).resp.bits.s1.entry.tag, 0.U(sectortlbwidth.W)) 461 difftest.pbmt := io.tlb(i).resp.bits.s1.entry.pbmt 462 difftest.g_pbmt := io.tlb(i).resp.bits.s2.entry.pbmt 463 for (j <- 0 until tlbcontiguous) { 464 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.s1.entry.ppn, io.tlb(i).resp.bits.s1.ppn_low(j)) 465 difftest.valididx(j) := io.tlb(i).resp.bits.s1.valididx(j) 466 difftest.pteidx(j) := io.tlb(i).resp.bits.s1.pteidx(j) 467 } 468 difftest.perm := io.tlb(i).resp.bits.s1.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 469 difftest.level := io.tlb(i).resp.bits.s1.entry.level.getOrElse(0.U.asUInt) 470 difftest.pf := io.tlb(i).resp.bits.s1.pf 471 difftest.satp := Cat(io.csr.tlb.satp.mode, io.csr.tlb.satp.asid, io.csr.tlb.satp.ppn) 472 difftest.vsatp := Cat(io.csr.tlb.vsatp.mode, io.csr.tlb.vsatp.asid, io.csr.tlb.vsatp.ppn) 473 difftest.hgatp := Cat(io.csr.tlb.hgatp.mode, io.csr.tlb.hgatp.vmid, io.csr.tlb.hgatp.ppn) 474 difftest.gvpn := io.tlb(i).resp.bits.s2.entry.tag 475 difftest.g_perm := io.tlb(i).resp.bits.s2.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 476 difftest.g_level := io.tlb(i).resp.bits.s2.entry.level.getOrElse(0.U.asUInt) 477 difftest.s2ppn := io.tlb(i).resp.bits.s2.entry.ppn 478 difftest.gpf := io.tlb(i).resp.bits.s2.gpf 479 difftest.s2xlate := io.tlb(i).resp.bits.s2xlate 480 } 481 } 482 483 // pmp 484 pmp_check(0).req <> ptw.io.pmp.req 485 ptw.io.pmp.resp <> pmp_check(0).resp 486 pmp_check(1).req <> llptw.io.pmp.req 487 llptw.io.pmp.resp <> pmp_check(1).resp 488 pmp_check(2).req <> hptw.io.pmp.req 489 hptw.io.pmp.resp <> pmp_check(2).resp 490 491 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 492 493 // hptw and page cache -> ptw and llptw 494 val HptwRespArbCachePort = 0 495 val HptwRespArbHptw = 1 496 hptw_resp_arb.io.in(HptwRespArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.isHptwReq 497 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.id := cache.io.resp.bits.toHptw.id 498 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.resp := cache.io.resp.bits.toHptw.resp 499 hptw_resp_arb.io.in(HptwRespArbHptw).valid := hptw.io.resp.valid 500 hptw_resp_arb.io.in(HptwRespArbHptw).bits.id := hptw.io.resp.bits.id 501 hptw_resp_arb.io.in(HptwRespArbHptw).bits.resp := hptw.io.resp.bits.resp 502 hptw.io.resp.ready := hptw_resp_arb.io.in(HptwRespArbHptw).ready 503 504 ptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id === FsmReqID.U 505 ptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 506 llptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id =/= FsmReqID.U 507 llptw.io.hptw.resp.bits.id := hptw_resp_arb.io.out.bits.id 508 llptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 509 hptw_resp_arb.io.out.ready := true.B 510 511 // Timing: Maybe need to do some optimization or even add one more cycle 512 for (i <- 0 until PtwWidth) { 513 mergeArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U && !cache.io.resp.bits.isHptwReq 514 mergeArb(i).in(outArbCachePort).bits.s2xlate := cache.io.resp.bits.req_info.s2xlate 515 mergeArb(i).in(outArbCachePort).bits.s1 := cache.io.resp.bits.stage1 516 mergeArb(i).in(outArbCachePort).bits.s2 := cache.io.resp.bits.toHptw.resp 517 mergeArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 518 mergeArb(i).in(outArbFsmPort).bits.s2xlate := ptw.io.resp.bits.s2xlate 519 mergeArb(i).in(outArbFsmPort).bits.s1 := ptw.io.resp.bits.resp 520 mergeArb(i).in(outArbFsmPort).bits.s2 := ptw.io.resp.bits.h_resp 521 mergeArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 522 mergeArb(i).in(outArbMqPort).bits.s2xlate := llptw_out.bits.req_info.s2xlate 523 mergeArb(i).in(outArbMqPort).bits.s1 := Mux( 524 llptw_out.bits.first_s2xlate_fault, llptw_stage1(llptw_out.bits.id), 525 contiguous_pte_to_merge_ptwResp( 526 resp_pte_sector(llptw_out.bits.id).asUInt, llptw_out.bits.req_info.vpn, llptw_out.bits.af, 527 true, s2xlate = llptw_out.bits.req_info.s2xlate, mPBMTE = mPBMTE, hPBMTE = hPBMTE, gpf = llptw_out.bits.h_resp.gpf 528 ) 529 ) 530 mergeArb(i).in(outArbMqPort).bits.s2 := llptw_out.bits.h_resp 531 mergeArb(i).out.ready := outArb(i).in(0).ready 532 } 533 534 for (i <- 0 until PtwWidth) { 535 outArb(i).in(0).valid := mergeArb(i).out.valid 536 outArb(i).in(0).bits.s2xlate := mergeArb(i).out.bits.s2xlate 537 outArb(i).in(0).bits.s1 := merge_ptwResp_to_sector_ptwResp(mergeArb(i).out.bits.s1) 538 outArb(i).in(0).bits.s2 := mergeArb(i).out.bits.s2 539 } 540 541 // io.tlb.map(_.resp) <> outArb.map(_.out) 542 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 543 case (resp, out) => resp <> out 544 } 545 546 // sfence 547 when (flush) { 548 for (i <- 0 until MemReqWidth) { 549 when (waiting_resp(i)) { 550 flush_latch(i) := true.B 551 } 552 } 553 } 554 // mem -> control signal 555 // waiting_resp and sfence_latch will be reset when mem_resp_done 556 when (mem_resp_done) { 557 waiting_resp(mem.d.bits.source) := false.B 558 flush_latch(mem.d.bits.source) := false.B 559 } 560 561 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 562 sink.valid := source.valid && !block_signal 563 source.ready := sink.ready && !block_signal 564 sink.bits := source.bits 565 } 566 567 def get_part(data: Vec[UInt], index: UInt): UInt = { 568 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 569 inner_data(index) 570 } 571 572 // not_super means that this is a normal page 573 // valididx(i) will be all true when super page to be convenient for l1 tlb matching 574 def contiguous_pte_to_merge_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean, s2xlate: UInt, mPBMTE: Bool, hPBMTE: Bool, not_super: Boolean = true, gpf: Bool) : PtwMergeResp = { 575 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 576 val ptw_merge_resp = Wire(new PtwMergeResp()) 577 val hasS2xlate = s2xlate =/= noS2xlate 578 val pbmte = Mux(s2xlate === onlyStage1 || s2xlate === allStage, hPBMTE, mPBMTE) 579 for (i <- 0 until tlbcontiguous) { 580 val pte_in = pte(64 * i + 63, 64 * i).asTypeOf(new PteBundle()) 581 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true, hasNapot = true)) 582 ptw_resp.ppn := pte_in.getPPN()(ptePPNLen - 1, sectortlbwidth) 583 ptw_resp.ppn_low := pte_in.getPPN()(sectortlbwidth - 1, 0) 584 ptw_resp.level.map(_ := 0.U) 585 ptw_resp.pbmt := pte_in.pbmt 586 ptw_resp.n.map(_ := pte_in.n) 587 ptw_resp.perm.map(_ := pte_in.getPerm()) 588 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 589 ptw_resp.pf := (if (af_first) !af else true.B) && (pte_in.isPf(0.U, pbmte) || !pte_in.isLeaf()) 590 ptw_resp.af := (if (!af_first) pte_in.isPf(0.U, pbmte) else true.B) && (af || (Mux(s2xlate === allStage, false.B, pte_in.isAf()) && !(hasS2xlate && gpf))) 591 ptw_resp.v := !ptw_resp.pf 592 ptw_resp.prefetch := DontCare 593 ptw_resp.asid := Mux(hasS2xlate, vsatp.asid, satp.asid) 594 ptw_resp.vmid.map(_ := hgatp.vmid) 595 ptw_merge_resp.entry(i) := ptw_resp 596 } 597 ptw_merge_resp.pteidx := UIntToOH(vpn(sectortlbwidth - 1, 0)).asBools 598 ptw_merge_resp.not_super := not_super.B 599 ptw_merge_resp.not_merge := hasS2xlate 600 ptw_merge_resp 601 } 602 603 def merge_ptwResp_to_sector_ptwResp(pte: PtwMergeResp) : PtwSectorResp = { 604 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 605 val ptw_sector_resp = Wire(new PtwSectorResp) 606 ptw_sector_resp.entry.tag := pte.entry(OHToUInt(pte.pteidx)).tag 607 ptw_sector_resp.entry.asid := pte.entry(OHToUInt(pte.pteidx)).asid 608 ptw_sector_resp.entry.vmid.map(_ := pte.entry(OHToUInt(pte.pteidx)).vmid.getOrElse(0.U)) 609 ptw_sector_resp.entry.ppn := pte.entry(OHToUInt(pte.pteidx)).ppn 610 ptw_sector_resp.entry.pbmt := pte.entry(OHToUInt(pte.pteidx)).pbmt 611 ptw_sector_resp.entry.n.map(_ := pte.entry(OHToUInt(pte.pteidx)).n.getOrElse(0.U)) 612 ptw_sector_resp.entry.perm.map(_ := pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle))) 613 ptw_sector_resp.entry.level.map(_ := pte.entry(OHToUInt(pte.pteidx)).level.getOrElse(0.U(log2Up(Level + 1).W))) 614 ptw_sector_resp.entry.prefetch := pte.entry(OHToUInt(pte.pteidx)).prefetch 615 ptw_sector_resp.entry.v := pte.entry(OHToUInt(pte.pteidx)).v 616 ptw_sector_resp.af := pte.entry(OHToUInt(pte.pteidx)).af 617 ptw_sector_resp.pf := pte.entry(OHToUInt(pte.pteidx)).pf 618 ptw_sector_resp.addr_low := OHToUInt(pte.pteidx) 619 ptw_sector_resp.pteidx := pte.pteidx 620 for (i <- 0 until tlbcontiguous) { 621 val ppn_equal = pte.entry(i).ppn === pte.entry(OHToUInt(pte.pteidx)).ppn 622 val pbmt_equal = pte.entry(i).pbmt === pte.entry(OHToUInt(pte.pteidx)).pbmt 623 val n_equal = pte.entry(i).n.getOrElse(0.U) === pte.entry(OHToUInt(pte.pteidx)).n.getOrElse(0.U) 624 val perm_equal = pte.entry(i).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt === pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 625 val v_equal = pte.entry(i).v === pte.entry(OHToUInt(pte.pteidx)).v 626 val af_equal = pte.entry(i).af === pte.entry(OHToUInt(pte.pteidx)).af 627 val pf_equal = pte.entry(i).pf === pte.entry(OHToUInt(pte.pteidx)).pf 628 ptw_sector_resp.valididx(i) := ((ppn_equal && pbmt_equal && n_equal && perm_equal && v_equal && af_equal && pf_equal) || !pte.not_super) && !pte.not_merge 629 ptw_sector_resp.ppn_low(i) := pte.entry(i).ppn_low 630 } 631 ptw_sector_resp.valididx(OHToUInt(pte.pteidx)) := true.B 632 ptw_sector_resp 633 } 634 635 def outReady(source: UInt, port: Int): Bool = { 636 MuxLookup(source, true.B)((0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready)) 637 } 638 639 // debug info 640 for (i <- 0 until PtwWidth) { 641 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 642 } 643 XSDebug(p"[sfence] ${io.sfence}\n") 644 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 645 646 for (i <- 0 until PtwWidth) { 647 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire) 648 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 649 } 650 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 651 for (i <- 0 until (MemReqWidth + 1)) { 652 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 653 } 654 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 655 XSPerfAccumulate("mem_count", mem.a.fire) 656 for (i <- 0 until PtwWidth) { 657 XSPerfAccumulate(s"llptw_ppn_af${i}", mergeArb(i).in(outArbMqPort).valid && mergeArb(i).in(outArbMqPort).bits.s1.entry(OHToUInt(mergeArb(i).in(outArbMqPort).bits.s1.pteidx)).af && !llptw_out.bits.af) 658 XSPerfAccumulate(s"access_fault${i}", io.tlb(i).resp.fire && io.tlb(i).resp.bits.s1.af) 659 } 660 661 // print configs 662 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l2:${l2tlbParams.l2Size} fa l1: nSets ${l2tlbParams.l1nSets} nWays ${l2tlbParams.l1nWays} l0: ${l2tlbParams.l0nSets} nWays ${l2tlbParams.l0nWays} blockBytes:${l2tlbParams.blockBytes}") 663 664 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 665 generatePerfEvent() 666 667 val isWriteL1TlbTable = Constantin.createRecord(s"isWriteL1TlbTable$hartId") 668 val L1TlbTable = ChiselDB.createTable(s"L1Tlb_hart$hartId", new L1TlbDB) 669 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 670 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 671 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 672 ITlbRespDB.vpn := Cat(io.tlb(0).resp.bits.s1.entry.tag, OHToUInt(io.tlb(0).resp.bits.s1.pteidx)) 673 DTlbRespDB.vpn := Cat(io.tlb(1).resp.bits.s1.entry.tag, OHToUInt(io.tlb(1).resp.bits.s1.pteidx)) 674 L1TlbTable.log(ITlbReqDB, isWriteL1TlbTable.orR && io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 675 L1TlbTable.log(DTlbReqDB, isWriteL1TlbTable.orR && io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 676 L1TlbTable.log(ITlbRespDB, isWriteL1TlbTable.orR && io.tlb(0).resp.fire, "ITlbResp", clock, reset) 677 L1TlbTable.log(DTlbRespDB, isWriteL1TlbTable.orR && io.tlb(1).resp.fire, "DTlbResp", clock, reset) 678 679 val isWritePageCacheTable = Constantin.createRecord(s"isWritePageCacheTable$hartId") 680 val PageCacheTable = ChiselDB.createTable(s"PageCache_hart$hartId", new PageCacheDB) 681 val PageCacheDB = Wire(new PageCacheDB) 682 PageCacheDB.vpn := Cat(cache.io.resp.bits.stage1.entry(0).tag, OHToUInt(cache.io.resp.bits.stage1.pteidx)) 683 PageCacheDB.source := cache.io.resp.bits.req_info.source 684 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 685 PageCacheDB.is_first := cache.io.resp.bits.isFirst 686 PageCacheDB.prefetched := cache.io.resp.bits.stage1.entry(0).prefetch 687 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 688 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 689 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 690 PageCacheDB.hit := cache.io.resp.bits.hit 691 PageCacheTable.log(PageCacheDB, isWritePageCacheTable.orR && cache.io.resp.fire, "PageCache", clock, reset) 692 693 val isWritePTWTable = Constantin.createRecord(s"isWritePTWTable$hartId") 694 val PTWTable = ChiselDB.createTable(s"PTW_hart$hartId", new PTWDB) 695 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 696 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 697 PTWReqDB.source := ptw.io.req.bits.req_info.source 698 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 699 PTWRespDB.source := ptw.io.refill.req_info.source 700 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 701 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 702 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 703 LLPTWRespDB.source := llptw.io.mem.refill.source 704 PTWTable.log(PTWReqDB, isWritePTWTable.orR && ptw.io.req.fire, "PTWReq", clock, reset) 705 PTWTable.log(PTWRespDB, isWritePTWTable.orR && ptw.io.mem.resp.fire, "PTWResp", clock, reset) 706 PTWTable.log(LLPTWReqDB, isWritePTWTable.orR && llptw.io.in.fire, "LLPTWReq", clock, reset) 707 PTWTable.log(LLPTWRespDB, isWritePTWTable.orR && llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 708 709 val isWriteL2TlbMissQueueTable = Constantin.createRecord(s"isWriteL2TlbMissQueueTable$hartId") 710 val L2TlbMissQueueTable = ChiselDB.createTable(s"L2TlbMissQueue_hart$hartId", new L2TlbMissQueueDB) 711 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 712 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.req_info.vpn 713 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.req_info.vpn 714 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 715 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 716} 717 718/** BlockHelper, block missqueue, not to send too many req to cache 719 * Parameter: 720 * enable: enable BlockHelper, mq should not send too many reqs 721 * start: when miss queue out fire and need, block miss queue's out 722 * block: block miss queue's out 723 * latency: last missqueue out's cache access latency 724 */ 725class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 726 val io = IO(new Bundle { 727 val enable = Input(Bool()) 728 val start = Input(Bool()) 729 val block = Output(Bool()) 730 }) 731 732 val count = RegInit(0.U(log2Ceil(latency).W)) 733 val valid = RegInit(false.B) 734 val work = RegInit(true.B) 735 736 io.block := valid 737 738 when (io.start && work) { valid := true.B } 739 when (valid) { count := count + 1.U } 740 when (count === (latency.U) || io.enable) { 741 valid := false.B 742 work := io.enable 743 count := 0.U 744 } 745} 746 747class PTEHelper() extends ExtModule { 748 val clock = IO(Input(Clock())) 749 val enable = IO(Input(Bool())) 750 val satp = IO(Input(UInt(64.W))) 751 val vpn = IO(Input(UInt(64.W))) 752 val pte = IO(Output(UInt(64.W))) 753 val level = IO(Output(UInt(8.W))) 754 val pf = IO(Output(UInt(8.W))) 755} 756 757class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 758 val io = IO(new Bundle() { 759 val in = Input(gen) 760 val out = Output(gen) 761 val ptwflush = Input(flush.cloneType) 762 }) 763 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 764 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 765 out(0) := io.in 766 if (n == 1) { 767 io.out := out(0) 768 } else { 769 when (io.ptwflush) { 770 for (i <- 0 until n) { 771 t(i) := 0.U.asTypeOf(gen) 772 out(i) := 0.U.asTypeOf(gen) 773 } 774 io.out := 0.U.asTypeOf(gen) 775 } .otherwise { 776 for (i <- 1 until n) { 777 t(i-1) := out(i-1) 778 out(i) := t(i-1) 779 } 780 io.out := out(n-1) 781 } 782 } 783} 784 785object PTWDelayN { 786 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 787 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 788 delay.io.in := in 789 delay.io.ptwflush := flush 790 delay.io.out 791 } 792} 793 794class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 795 val io = IO(new L2TLBIO) 796 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 797 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 798 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 799 for (i <- 0 until PtwWidth) { 800 val helper = Module(new PTEHelper()) 801 helper.clock := clock 802 helper.satp := io.csr.tlb.satp.ppn 803 804 if (coreParams.softPTWDelay == 1) { 805 helper.enable := io.tlb(i).req(0).fire 806 helper.vpn := io.tlb(i).req(0).bits.vpn 807 } else { 808 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 809 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 810 } 811 812 val pte = helper.pte.asTypeOf(new PteBundle) 813 val level = helper.level 814 val pf = helper.pf 815 val empty = RegInit(true.B) 816 when (io.tlb(i).req(0).fire) { 817 empty := false.B 818 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 819 empty := true.B 820 } 821 822 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 823 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 824 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 825 io.tlb(i).resp.bits.s1.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 826 io.tlb(i).resp.bits.s1.entry.pbmt := pte.pbmt 827 io.tlb(i).resp.bits.s1.entry.ppn := pte.ppn 828 io.tlb(i).resp.bits.s1.entry.perm.map(_ := pte.getPerm()) 829 io.tlb(i).resp.bits.s1.entry.level.map(_ := level) 830 io.tlb(i).resp.bits.s1.pf := pf 831 io.tlb(i).resp.bits.s1.af := DontCare // TODO: implement it 832 io.tlb(i).resp.bits.s1.entry.v := !pf 833 io.tlb(i).resp.bits.s1.entry.prefetch := DontCare 834 io.tlb(i).resp.bits.s1.entry.asid := io.csr.tlb.satp.asid 835 } 836} 837 838class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 839 override def shouldBeInlined: Boolean = false 840 val useSoftPTW = coreParams.softPTW 841 val node = if (!useSoftPTW) TLIdentityNode() else null 842 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 843 if (!useSoftPTW) { 844 node := ptw.node 845 } 846 847 class L2TLBWrapperImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasPerfEvents { 848 val io = IO(new L2TLBIO) 849 val perfEvents = if (useSoftPTW) { 850 val fake_ptw = Module(new FakePTW()) 851 io <> fake_ptw.io 852 Seq() 853 } 854 else { 855 io <> ptw.module.io 856 ptw.module.getPerfEvents 857 } 858 generatePerfEvent() 859 } 860 861 lazy val module = new L2TLBWrapperImp(this) 862} 863