1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31import difftest._ 32 33class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 34 override def shouldBeInlined: Boolean = false 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )), 41 requestFields = Seq(ReqSourceField()) 42 ))) 43 44 lazy val module = new L2TLBImp(this) 45} 46 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(8)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(7)(RegNext(csr_tmp)) 83 val satp = csr_dup(0).satp 84 val priv = csr_dup(0).priv 85 val flush = sfence_dup(0).valid || satp.changed 86 87 val pmp = Module(new PMP()) 88 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 89 pmp.io.distribute_csr := io.csr.distribute_csr 90 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 91 92 val missQueue = Module(new L2TlbMissQueue) 93 val cache = Module(new PtwCache) 94 val ptw = Module(new PTW) 95 val llptw = Module(new LLPTW) 96 val blockmq = Module(new BlockHelper(3)) 97 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 98 val arb2 = Module(new Arbiter(new Bundle { 99 val vpn = UInt(vpnLen.W) 100 val source = UInt(bSourceWidth.W) 101 }, if (l2tlbParams.enablePrefetch) 4 else 3)) 102 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwSectorResp, 1)).io) 103 val mergeArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwMergeResp, 3)).io) 104 val outArbCachePort = 0 105 val outArbFsmPort = 1 106 val outArbMqPort = 2 107 108 // arb2 input port 109 val InArbPTWPort = 0 110 val InArbMissQueuePort = 1 111 val InArbTlbPort = 2 112 val InArbPrefetchPort = 3 113 // NOTE: when cache out but miss and ptw doesnt accept, 114 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 115 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 116 117 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 118 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 119 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 120 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 121 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 122 123 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 124 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 125 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 126 if (l2tlbParams.enablePrefetch) { 127 val prefetch = Module(new L2TlbPrefetch()) 128 val recv = cache.io.resp 129 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 130 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 131 prefetch.io.in.valid := recv.fire && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 132 recv.bits.prefetch) && recv.bits.isFirst 133 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 134 prefetch.io.sfence := sfence_dup(0) 135 prefetch.io.csr := csr_dup(0) 136 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 137 138 val isWriteL2TlbPrefetchTable = WireInit(Constantin.createRecord("isWriteL2TlbPrefetchTable" + p(XSCoreParamsKey).HartId.toString)) 139 val L2TlbPrefetchTable = ChiselDB.createTable("L2TlbPrefetch_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbPrefetchDB) 140 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 141 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.vpn 142 L2TlbPrefetchTable.log(L2TlbPrefetchDB, isWriteL2TlbPrefetchTable.orR && prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 143 } 144 arb2.io.out.ready := cache.io.req.ready 145 146 147 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 148 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 149 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 150 !from_pre(cache.io.resp.bits.req_info.source) && 151 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 152 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 153 mq_arb.io.in(1) <> llptw.io.cache 154 missQueue.io.in <> mq_arb.io.out 155 missQueue.io.sfence := sfence_dup(6) 156 missQueue.io.csr := csr_dup(5) 157 158 blockmq.io.start := missQueue.io.out.fire 159 blockmq.io.enable := ptw.io.req.fire 160 161 llptw.io.in.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed 162 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 163 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 164 llptw.io.sfence := sfence_dup(1) 165 llptw.io.csr := csr_dup(1) 166 167 cache.io.req.valid := arb2.io.out.valid 168 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 169 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 170 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 171 cache.io.req.bits.bypassed.map(_ := false.B) 172 cache.io.sfence := sfence_dup(2) 173 cache.io.csr := csr_dup(2) 174 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 175 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 176 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 177 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 178 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 179 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 180 181 // NOTE: missQueue req has higher priority 182 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 183 !cache.io.resp.bits.bypassed && 184 !cache.io.resp.bits.isFirst 185 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 186 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 187 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 188 ptw.io.sfence := sfence_dup(7) 189 ptw.io.csr := csr_dup(6) 190 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 191 192 // mem req 193 def blockBytes_align(addr: UInt) = { 194 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 195 } 196 def addr_low_from_vpn(vpn: UInt) = { 197 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 198 } 199 def addr_low_from_paddr(paddr: UInt) = { 200 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 201 } 202 def from_missqueue(id: UInt) = { 203 (id =/= l2tlbParams.llptwsize.U) 204 } 205 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 206 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 207 for (i <- waiting_resp.indices) { 208 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 209 } 210 211 val llptw_out = llptw.io.out 212 val llptw_mem = llptw.io.mem 213 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 214 ptw.io.mem.mask := waiting_resp.last 215 216 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 2)) 217 mem_arb.io.in(0) <> ptw.io.mem.req 218 mem_arb.io.in(1) <> llptw_mem.req 219 mem_arb.io.out.ready := mem.a.ready && !flush 220 221 // assert, should not send mem access at same addr for twice. 222 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 223 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 224 val last_resp_v = RegInit(false.B) 225 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR || cache.io.refill.bits.sel_pte_dup(0).asTypeOf(new PteBundle).isAf() 226 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 227 when (flush) { last_resp_v := false.B } 228 XSError(last_resp_v && cache.io.refill.valid && 229 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 230 (cache.io.refill.bits.level_dup(0) === last_resp_level), 231 "l2tlb should not access mem at same addr for twice") 232 // ATTENTION: this may wronngly assert when: a ptes is l2, last part is valid, 233 // but the current part is invalid, so one more mem access happened 234 // If this happened, remove the assert. 235 236 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 237 238 when (llptw.io.in.fire) { 239 // when enq miss queue, set the req_addr_low to receive the mem resp data part 240 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 241 } 242 when (mem_arb.io.out.fire) { 243 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 244 waiting_resp(mem_arb.io.out.bits.id) := true.B 245 } 246 // mem read 247 val memRead = edge.Get( 248 fromSource = mem_arb.io.out.bits.id, 249 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 250 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 251 lgSize = log2Up(l2tlbParams.blockBytes).U 252 )._2 253 mem.a.bits := memRead 254 mem.a.valid := mem_arb.io.out.valid && !flush 255 mem.a.bits.user.lift(ReqSourceKey).foreach(_ := MemReqSource.PTW.id.U) 256 mem.d.ready := true.B 257 // mem -> data buffer 258 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 259 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire) 260 val mem_resp_done = refill_helper._3 261 val mem_resp_from_mq = from_missqueue(mem.d.bits.source) 262 when (mem.d.valid) { 263 assert(mem.d.bits.source <= l2tlbParams.llptwsize.U) 264 refill_data(refill_helper._4) := mem.d.bits.data 265 } 266 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 267 val refill_data_tmp = WireInit(refill_data) 268 refill_data_tmp(refill_helper._4) := mem.d.bits.data 269 270 // save only one pte for each id 271 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 272 val resp_pte = VecInit((0 until MemReqWidth).map(i => 273 if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && !mem_resp_from_mq) } 274 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 275 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 276 )) 277 278 // save eight ptes for each id when sector tlb 279 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 280 val resp_pte_sector = VecInit((0 until MemReqWidth).map(i => 281 if (i == l2tlbParams.llptwsize) {RegEnable(refill_data_tmp, mem_resp_done && !mem_resp_from_mq) } 282 else { DataHoldBypass(refill_data, llptw_mem.buffer_it(i)) } 283 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 284 )) 285 286 // mem -> miss queue 287 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_mq 288 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 289 // mem -> ptw 290 ptw.io.mem.req.ready := mem.a.ready 291 ptw.io.mem.resp.valid := mem_resp_done && !mem_resp_from_mq 292 ptw.io.mem.resp.bits := resp_pte.last 293 // mem -> cache 294 val refill_from_mq = mem_resp_from_mq 295 val refill_level = Mux(refill_from_mq, 2.U, RegEnable(ptw.io.refill.level, 0.U, ptw.io.mem.req.fire)) 296 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 297 298 cache.io.refill.valid := RegNext(refill_valid, false.B) 299 cache.io.refill.bits.ptes := refill_data.asUInt 300 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_mq, llptw_mem.refill, ptw.io.refill.req_info), refill_valid)) 301 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 302 cache.io.refill.bits.levelOH(refill_level, refill_valid) 303 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 304 305 if (env.EnableDifftest) { 306 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W)))) 307 when (mem.a.valid) { 308 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address 309 } 310 311 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) 312 difftest.coreid := io.hartId 313 difftest.index := 2.U 314 difftest.valid := cache.io.refill.valid 315 difftest.addr := difftest_ptw_addr(RegNext(mem.d.bits.source)) 316 difftest.data := refill_data.asTypeOf(difftest.data) 317 difftest.idtfr := DontCare 318 } 319 320 if (env.EnableDifftest) { 321 for (i <- 0 until PtwWidth) { 322 val difftest = DifftestModule(new DiffL2TLBEvent) 323 difftest.coreid := io.hartId 324 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.af 325 difftest.index := i.U 326 difftest.satp := io.csr.tlb.satp.ppn 327 difftest.vpn := Cat(io.tlb(i).resp.bits.entry.tag, 0.U(sectortlbwidth.W)) 328 for (j <- 0 until tlbcontiguous) { 329 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j)) 330 difftest.valididx(j) := io.tlb(i).resp.bits.valididx(j) 331 } 332 difftest.perm := io.tlb(i).resp.bits.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 333 difftest.level := io.tlb(i).resp.bits.entry.level.getOrElse(0.U.asUInt) 334 difftest.pf := io.tlb(i).resp.bits.pf 335 } 336 } 337 338 // pmp 339 pmp_check(0).req <> ptw.io.pmp.req 340 ptw.io.pmp.resp <> pmp_check(0).resp 341 pmp_check(1).req <> llptw.io.pmp.req 342 llptw.io.pmp.resp <> pmp_check(1).resp 343 344 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 345 346 // Timing: Maybe need to do some optimization or even add one more cycle 347 for (i <- 0 until PtwWidth) { 348 mergeArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 349 mergeArb(i).in(outArbCachePort).bits := cache.io.resp.bits.toTlb 350 mergeArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 351 mergeArb(i).in(outArbFsmPort).bits := ptw.io.resp.bits.resp 352 mergeArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 353 mergeArb(i).in(outArbMqPort).bits := contiguous_pte_to_merge_ptwResp(resp_pte_sector(llptw_out.bits.id).asUInt, llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 354 mergeArb(i).out.ready := outArb(i).in(0).ready 355 } 356 357 for (i <- 0 until PtwWidth) { 358 outArb(i).in(0).valid := mergeArb(i).out.valid 359 outArb(i).in(0).bits := merge_ptwResp_to_sector_ptwResp(mergeArb(i).out.bits) 360 } 361 362 // io.tlb.map(_.resp) <> outArb.map(_.out) 363 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 364 case (resp, out) => resp <> out 365 } 366 367 // sfence 368 when (flush) { 369 for (i <- 0 until MemReqWidth) { 370 when (waiting_resp(i)) { 371 flush_latch(i) := true.B 372 } 373 } 374 } 375 // mem -> control signal 376 // waiting_resp and sfence_latch will be reset when mem_resp_done 377 when (mem_resp_done) { 378 waiting_resp(mem.d.bits.source) := false.B 379 flush_latch(mem.d.bits.source) := false.B 380 } 381 382 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 383 sink.valid := source.valid && !block_signal 384 source.ready := sink.ready && !block_signal 385 sink.bits := source.bits 386 } 387 388 def get_part(data: Vec[UInt], index: UInt): UInt = { 389 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 390 inner_data(index) 391 } 392 393 def pte_to_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean) : PtwResp = { 394 val pte_in = pte.asTypeOf(new PteBundle()) 395 val ptw_resp = Wire(new PtwResp()) 396 ptw_resp.entry.ppn := pte_in.ppn 397 ptw_resp.entry.level.map(_ := 2.U) 398 ptw_resp.entry.perm.map(_ := pte_in.getPerm()) 399 ptw_resp.entry.tag := vpn 400 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 401 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && (af || pte_in.isAf()) 402 ptw_resp.entry.v := !ptw_resp.pf 403 ptw_resp.entry.prefetch := DontCare 404 ptw_resp.entry.asid := satp.asid 405 ptw_resp 406 } 407 408 // not_super means that this is a normal page 409 // valididx(i) will be all true when super page to be convenient for l1 tlb matching 410 def contiguous_pte_to_merge_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean, not_super: Boolean = true) : PtwMergeResp = { 411 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 412 val ptw_merge_resp = Wire(new PtwMergeResp()) 413 for (i <- 0 until tlbcontiguous) { 414 val pte_in = pte(64 * i + 63, 64 * i).asTypeOf(new PteBundle()) 415 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 416 ptw_resp.ppn := pte_in.ppn(ppnLen - 1, sectortlbwidth) 417 ptw_resp.ppn_low := pte_in.ppn(sectortlbwidth - 1, 0) 418 ptw_resp.level.map(_ := 2.U) 419 ptw_resp.perm.map(_ := pte_in.getPerm()) 420 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 421 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 422 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && (af || pte_in.isAf()) 423 ptw_resp.v := !ptw_resp.pf 424 ptw_resp.prefetch := DontCare 425 ptw_resp.asid := satp.asid 426 ptw_merge_resp.entry(i) := ptw_resp 427 } 428 ptw_merge_resp.pteidx := UIntToOH(vpn(sectortlbwidth - 1, 0)).asBools 429 ptw_merge_resp.not_super := not_super.B 430 ptw_merge_resp 431 } 432 433 def merge_ptwResp_to_sector_ptwResp(pte: PtwMergeResp) : PtwSectorResp = { 434 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 435 val ptw_sector_resp = Wire(new PtwSectorResp) 436 ptw_sector_resp.entry.tag := pte.entry(OHToUInt(pte.pteidx)).tag 437 ptw_sector_resp.entry.asid := pte.entry(OHToUInt(pte.pteidx)).asid 438 ptw_sector_resp.entry.ppn := pte.entry(OHToUInt(pte.pteidx)).ppn 439 ptw_sector_resp.entry.perm.map(_ := pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle))) 440 ptw_sector_resp.entry.level.map(_ := pte.entry(OHToUInt(pte.pteidx)).level.getOrElse(0.U(2.W))) 441 ptw_sector_resp.entry.prefetch := pte.entry(OHToUInt(pte.pteidx)).prefetch 442 ptw_sector_resp.entry.v := pte.entry(OHToUInt(pte.pteidx)).v 443 ptw_sector_resp.af := pte.entry(OHToUInt(pte.pteidx)).af 444 ptw_sector_resp.pf := pte.entry(OHToUInt(pte.pteidx)).pf 445 ptw_sector_resp.addr_low := OHToUInt(pte.pteidx) 446 ptw_sector_resp.pteidx := pte.pteidx 447 for (i <- 0 until tlbcontiguous) { 448 val ppn_equal = pte.entry(i).ppn === pte.entry(OHToUInt(pte.pteidx)).ppn 449 val perm_equal = pte.entry(i).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt === pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 450 val v_equal = pte.entry(i).v === pte.entry(OHToUInt(pte.pteidx)).v 451 val af_equal = pte.entry(i).af === pte.entry(OHToUInt(pte.pteidx)).af 452 val pf_equal = pte.entry(i).pf === pte.entry(OHToUInt(pte.pteidx)).pf 453 ptw_sector_resp.valididx(i) := (ppn_equal && perm_equal && v_equal && af_equal && pf_equal) || !pte.not_super 454 ptw_sector_resp.ppn_low(i) := pte.entry(i).ppn_low 455 } 456 ptw_sector_resp.valididx(OHToUInt(pte.pteidx)) := true.B 457 ptw_sector_resp 458 } 459 460 def outReady(source: UInt, port: Int): Bool = { 461 MuxLookup(source, true.B, 462 (0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready)) 463 } 464 465 // debug info 466 for (i <- 0 until PtwWidth) { 467 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 468 } 469 XSDebug(p"[sfence] ${io.sfence}\n") 470 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 471 472 for (i <- 0 until PtwWidth) { 473 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire) 474 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 475 } 476 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 477 for (i <- 0 until (MemReqWidth + 1)) { 478 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 479 } 480 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 481 XSPerfAccumulate("mem_count", mem.a.fire) 482 for (i <- 0 until PtwWidth) { 483 XSPerfAccumulate(s"llptw_ppn_af${i}", mergeArb(i).in(outArbMqPort).valid && mergeArb(i).in(outArbMqPort).bits.entry(OHToUInt(mergeArb(i).in(outArbMqPort).bits.pteidx)).af && !llptw_out.bits.af) 484 XSPerfAccumulate(s"access_fault${i}", io.tlb(i).resp.fire && io.tlb(i).resp.bits.af) 485 } 486 487 // print configs 488 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 489 490 // time out assert 491 for (i <- 0 until MemReqWidth) { 492 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 493 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 494 } 495 496 497 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 498 generatePerfEvent() 499 500 val isWriteL1TlbTable = WireInit(Constantin.createRecord("isWriteL1TlbTable" + p(XSCoreParamsKey).HartId.toString)) 501 val L1TlbTable = ChiselDB.createTable("L1Tlb_hart" + p(XSCoreParamsKey).HartId.toString, new L1TlbDB) 502 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 503 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 504 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 505 ITlbRespDB.vpn := io.tlb(0).resp.bits.entry.tag 506 DTlbRespDB.vpn := io.tlb(1).resp.bits.entry.tag 507 L1TlbTable.log(ITlbReqDB, isWriteL1TlbTable.orR && io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 508 L1TlbTable.log(DTlbReqDB, isWriteL1TlbTable.orR && io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 509 L1TlbTable.log(ITlbRespDB, isWriteL1TlbTable.orR && io.tlb(0).resp.fire, "ITlbResp", clock, reset) 510 L1TlbTable.log(DTlbRespDB, isWriteL1TlbTable.orR && io.tlb(1).resp.fire, "DTlbResp", clock, reset) 511 512 val isWritePageCacheTable = WireInit(Constantin.createRecord("isWritePageCacheTable" + p(XSCoreParamsKey).HartId.toString)) 513 val PageCacheTable = ChiselDB.createTable("PageCache_hart" + p(XSCoreParamsKey).HartId.toString, new PageCacheDB) 514 val PageCacheDB = Wire(new PageCacheDB) 515 PageCacheDB.vpn := Cat(cache.io.resp.bits.toTlb.entry(0).tag, OHToUInt(cache.io.resp.bits.toTlb.pteidx)) 516 PageCacheDB.source := cache.io.resp.bits.req_info.source 517 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 518 PageCacheDB.is_first := cache.io.resp.bits.isFirst 519 PageCacheDB.prefetched := cache.io.resp.bits.toTlb.entry(0).prefetch 520 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 521 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 522 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 523 PageCacheDB.hit := cache.io.resp.bits.hit 524 PageCacheTable.log(PageCacheDB, isWritePageCacheTable.orR && cache.io.resp.fire, "PageCache", clock, reset) 525 526 val isWritePTWTable = WireInit(Constantin.createRecord("isWritePTWTable" + p(XSCoreParamsKey).HartId.toString)) 527 val PTWTable = ChiselDB.createTable("PTW_hart" + p(XSCoreParamsKey).HartId.toString, new PTWDB) 528 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 529 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 530 PTWReqDB.source := ptw.io.req.bits.req_info.source 531 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 532 PTWRespDB.source := ptw.io.refill.req_info.source 533 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 534 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 535 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 536 LLPTWRespDB.source := llptw.io.mem.refill.source 537 PTWTable.log(PTWReqDB, isWritePTWTable.orR && ptw.io.req.fire, "PTWReq", clock, reset) 538 PTWTable.log(PTWRespDB, isWritePTWTable.orR && ptw.io.mem.resp.fire, "PTWResp", clock, reset) 539 PTWTable.log(LLPTWReqDB, isWritePTWTable.orR && llptw.io.in.fire, "LLPTWReq", clock, reset) 540 PTWTable.log(LLPTWRespDB, isWritePTWTable.orR && llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 541 542 val isWriteL2TlbMissQueueTable = WireInit(Constantin.createRecord("isWriteL2TlbMissQueueTable" + p(XSCoreParamsKey).HartId.toString)) 543 val L2TlbMissQueueTable = ChiselDB.createTable("L2TlbMissQueue_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbMissQueueDB) 544 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 545 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.vpn 546 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.vpn 547 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 548 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 549} 550 551/** BlockHelper, block missqueue, not to send too many req to cache 552 * Parameter: 553 * enable: enable BlockHelper, mq should not send too many reqs 554 * start: when miss queue out fire and need, block miss queue's out 555 * block: block miss queue's out 556 * latency: last missqueue out's cache access latency 557 */ 558class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 559 val io = IO(new Bundle { 560 val enable = Input(Bool()) 561 val start = Input(Bool()) 562 val block = Output(Bool()) 563 }) 564 565 val count = RegInit(0.U(log2Ceil(latency).W)) 566 val valid = RegInit(false.B) 567 val work = RegInit(true.B) 568 569 io.block := valid 570 571 when (io.start && work) { valid := true.B } 572 when (valid) { count := count + 1.U } 573 when (count === (latency.U) || io.enable) { 574 valid := false.B 575 work := io.enable 576 count := 0.U 577 } 578} 579 580class PTEHelper() extends ExtModule { 581 val clock = IO(Input(Clock())) 582 val enable = IO(Input(Bool())) 583 val satp = IO(Input(UInt(64.W))) 584 val vpn = IO(Input(UInt(64.W))) 585 val pte = IO(Output(UInt(64.W))) 586 val level = IO(Output(UInt(8.W))) 587 val pf = IO(Output(UInt(8.W))) 588} 589 590class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 591 val io = IO(new Bundle() { 592 val in = Input(gen) 593 val out = Output(gen) 594 val ptwflush = Input(flush.cloneType) 595 }) 596 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 597 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 598 out(0) := io.in 599 if (n == 1) { 600 io.out := out(0) 601 } else { 602 when (io.ptwflush) { 603 for (i <- 0 until n) { 604 t(i) := 0.U.asTypeOf(gen) 605 out(i) := 0.U.asTypeOf(gen) 606 } 607 io.out := 0.U.asTypeOf(gen) 608 } .otherwise { 609 for (i <- 1 until n) { 610 t(i-1) := out(i-1) 611 out(i) := t(i-1) 612 } 613 io.out := out(n-1) 614 } 615 } 616} 617 618object PTWDelayN { 619 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 620 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 621 delay.io.in := in 622 delay.io.ptwflush := flush 623 delay.io.out 624 } 625} 626 627class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 628 val io = IO(new L2TLBIO) 629 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 630 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 631 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 632 for (i <- 0 until PtwWidth) { 633 val helper = Module(new PTEHelper()) 634 helper.clock := clock 635 helper.satp := io.csr.tlb.satp.ppn 636 637 if (coreParams.softPTWDelay == 1) { 638 helper.enable := io.tlb(i).req(0).fire 639 helper.vpn := io.tlb(i).req(0).bits.vpn 640 } else { 641 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 642 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 643 } 644 645 val pte = helper.pte.asTypeOf(new PteBundle) 646 val level = helper.level 647 val pf = helper.pf 648 val empty = RegInit(true.B) 649 when (io.tlb(i).req(0).fire) { 650 empty := false.B 651 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 652 empty := true.B 653 } 654 655 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 656 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 657 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 658 io.tlb(i).resp.bits.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 659 io.tlb(i).resp.bits.entry.ppn := pte.ppn 660 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 661 io.tlb(i).resp.bits.entry.level.map(_ := level) 662 io.tlb(i).resp.bits.pf := pf 663 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 664 io.tlb(i).resp.bits.entry.v := !pf 665 io.tlb(i).resp.bits.entry.prefetch := DontCare 666 io.tlb(i).resp.bits.entry.asid := io.csr.tlb.satp.asid 667 } 668} 669 670class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 671 override def shouldBeInlined: Boolean = false 672 val useSoftPTW = coreParams.softPTW 673 val node = if (!useSoftPTW) TLIdentityNode() else null 674 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 675 if (!useSoftPTW) { 676 node := ptw.node 677 } 678 679 class L2TLBWrapperImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasPerfEvents { 680 val io = IO(new L2TLBIO) 681 val perfEvents = if (useSoftPTW) { 682 val fake_ptw = Module(new FakePTW()) 683 io <> fake_ptw.io 684 Seq() 685 } 686 else { 687 io <> ptw.module.io 688 ptw.module.getPerfEvents 689 } 690 generatePerfEvent() 691 } 692 693 lazy val module = new L2TLBWrapperImp(this) 694} 695