1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.rob.RobPtr 17import xiangshan.backend.datapath.NewPipelineConnect 18import xiangshan.backend.fu.vector.Bundles.VSew 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams: IssueBlockParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case FpScheduler() => new IssueQueueFpImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og2Resp = Option.when(params.inVfSchd)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val finalIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 57 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 58 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 59 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 60 val vlIsZero = Input(Bool()) 61 val vlIsVlmax = Input(Bool()) 62 val og0Cancel = Input(ExuVec()) 63 val og1Cancel = Input(ExuVec()) 64 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 65 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 66 67 // Outputs 68 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 69 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 70 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 71 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 72 73 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 74 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 75} 76 77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 78 extends LazyModuleImp(wrapper) 79 with HasXSParameter { 80 81 override def desiredName: String = s"${params.getIQName}" 82 83 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 84 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 85 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 86 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 87 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 88 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 89 90 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 91 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 92 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 93 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 94 95 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 96 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 97 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 98 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 99 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 100 101 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 102 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 103 lazy val io = IO(new IssueQueueIO()) 104 105 // Modules 106 val entries = Module(new Entries) 107 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 108 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 109 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 110 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 111 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 112 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 113 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 114 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 115 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 116 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 117 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 118 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 119 120 class WakeupQueueFlush extends Bundle { 121 val redirect = ValidIO(new Redirect) 122 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 123 val og0Fail = Output(Bool()) 124 val og1Fail = Output(Bool()) 125 } 126 127 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 128 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 129 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 130 val ogFailFlush = stage match { 131 case 1 => flush.og0Fail 132 case 2 => flush.og1Fail 133 case _ => false.B 134 } 135 redirectFlush || loadDependencyFlush || ogFailFlush 136 } 137 138 private def modificationFunc(exuInput: ExuInput): ExuInput = { 139 val newExuInput = WireDefault(exuInput) 140 newExuInput.loadDependency match { 141 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 142 case None => 143 } 144 newExuInput 145 } 146 147 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 148 val lastExuInput = WireDefault(exuInput) 149 val newExuInput = WireDefault(newInput) 150 newExuInput.elements.foreach { case (name, data) => 151 if (lastExuInput.elements.contains(name)) { 152 data := lastExuInput.elements(name) 153 } 154 } 155 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 156 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 157 } 158 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 159 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 160 } 161 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 162 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 163 } 164 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 165 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 166 } 167 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 168 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 169 } 170 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 171 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 172 } 173 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 174 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 175 } 176 newExuInput 177 } 178 179 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 180 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 181 ))} 182 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 183 184 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 185 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 186 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 187 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 188 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 189 190 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 191 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 192 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 193 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 194 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 195 196 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 197 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 198 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 199 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 200 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 201 202 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 209 val s0_enqValidVec = io.enq.map(_.valid) 210 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 211 val s0_enqNotFlush = !io.flush.valid 212 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 213 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 214 215 216 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 217 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 218 219 val validVec = VecInit(entries.io.valid.asBools) 220 val canIssueVec = VecInit(entries.io.canIssue.asBools) 221 dontTouch(canIssueVec) 222 val deqFirstIssueVec = entries.io.isFirstIssue 223 224 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 225 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 226 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 227 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 228 // (entryIdx)(srcIdx)(exuIdx) 229 val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH 230 // (deqIdx)(srcIdx)(exuIdx) 231 val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 232 233 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 234 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 235 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 236 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 237 238 //deq 239 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 240 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 241 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 242 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 243 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 244 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 245 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 246 247 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 248 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 249 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 250 251 //trans 252 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 253 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 254 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 255 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 256 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 257 258 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 259 // as vf exu's min latency is 1, we do not need consider og0cancel 260 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 261 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 262 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 263 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 264 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 265 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 266 } else { 267 w := w_src 268 } 269 } 270 271 /** 272 * Connection of [[entries]] 273 */ 274 entries.io match { case entriesIO: EntriesIO => 275 entriesIO.flush := io.flush 276 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 277 enq.valid := s0_doEnqSelValidVec(enqIdx) 278 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 279 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 280 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 281 for(j <- 0 until numLsrc) { 282 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 283 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 284 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 285 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 286 SrcState.rdy, 287 s0_enqBits(enqIdx).srcState(j)) 288 } else { 289 s0_enqBits(enqIdx).srcState(j) 290 }) 291 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 292 MuxCase(DataSource.reg, Seq( 293 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 294 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 295 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 296 )) 297 } else { 298 MuxCase(DataSource.reg, Seq( 299 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 300 )) 301 }) 302 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 303 if(params.hasIQWakeUp) { 304 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 305 } 306 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 307 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 308 } 309 enq.bits.status.blocked := false.B 310 enq.bits.status.issued := false.B 311 enq.bits.status.firstIssue := false.B 312 enq.bits.status.issueTimer := "b11".U 313 enq.bits.status.deqPortIdx := 0.U 314 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 315 enq.bits.payload := s0_enqBits(enqIdx) 316 } 317 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 318 og0Resp := io.og0Resp(i) 319 } 320 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 321 og1Resp := io.og1Resp(i) 322 } 323 if (params.inVfSchd) { 324 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 325 og2Resp := io.og2Resp.get(i) 326 } 327 } 328 if (params.isLdAddrIQ || params.isHyAddrIQ) { 329 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 330 finalIssueResp := io.finalIssueResp.get(i) 331 } 332 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 333 memAddrIssueResp := io.memAddrIssueResp.get(i) 334 } 335 } 336 if (params.isVecLduIQ) { 337 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 338 resp := io.vecLoadIssueResp.get(i) 339 } 340 } 341 for(deqIdx <- 0 until params.numDeq) { 342 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 343 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 344 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 345 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 346 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 347 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 348 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 349 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 350 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 351 } 352 entriesIO.wakeUpFromWB := io.wakeupFromWB 353 entriesIO.wakeUpFromIQ := wakeupFromIQ 354 entriesIO.vlIsZero := io.vlIsZero 355 entriesIO.vlIsVlmax := io.vlIsVlmax 356 entriesIO.og0Cancel := io.og0Cancel 357 entriesIO.og1Cancel := io.og1Cancel 358 entriesIO.ldCancel := io.ldCancel 359 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 360 //output 361 fuTypeVec := entriesIO.fuType 362 deqEntryVec := entriesIO.deqEntry 363 cancelDeqVec := entriesIO.cancelDeqVec 364 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 365 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 366 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 367 } 368 369 370 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 371 372 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 373 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 374 ).reverse) 375 376 // if deq port can accept the uop 377 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 378 Cat(fuTypeVec.map(fuType => 379 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 380 ).reverse) 381 } 382 383 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 384 fuTypeVec.map(fuType => 385 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 386 } 387 388 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 389 val mergeFuBusy = { 390 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 391 else canIssueVec.asUInt 392 } 393 val mergeIntWbBusy = { 394 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 395 else mergeFuBusy 396 } 397 val mergefpWbBusy = { 398 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 399 else mergeIntWbBusy 400 } 401 val mergeVfWbBusy = { 402 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 403 else mergefpWbBusy 404 } 405 val mergeV0WbBusy = { 406 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 407 else mergeVfWbBusy 408 } 409 val mergeVlWbBusy = { 410 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 411 else mergeV0WbBusy 412 } 413 merge := mergeVlWbBusy 414 } 415 416 deqCanIssue.zipWithIndex.foreach { case (req, i) => 417 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 418 } 419 dontTouch(fuTypeVec) 420 dontTouch(canIssueMergeAllBusy) 421 dontTouch(deqCanIssue) 422 423 if (params.numDeq == 2) { 424 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 425 } 426 427 if (params.numDeq == 2 && params.deqFuSame) { 428 val subDeqPolicy = Module(new DeqPolicy()) 429 430 enqEntryOldestSel := DontCare 431 432 if (params.isAllComp || params.isAllSimp) { 433 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 434 enq = othersEntryEnqSelVec.get, 435 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 436 ) 437 othersEntryOldestSel(1) := DontCare 438 439 subDeqPolicy.io.request := subDeqRequest.get 440 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 441 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 442 } 443 else { 444 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 445 simpAgeDetectRequest.get(1) := DontCare 446 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 447 if (params.numEnq == 2) { 448 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 449 } 450 451 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 452 enq = simpEntryEnqSelVec.get, 453 canIssue = simpAgeDetectRequest.get 454 ) 455 456 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 457 enq = compEntryEnqSelVec.get, 458 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 459 ) 460 compEntryOldestSel.get(1) := DontCare 461 462 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 463 othersEntryOldestSel(0).bits := Cat( 464 compEntryOldestSel.get(0).bits, 465 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 466 ) 467 othersEntryOldestSel(1) := DontCare 468 469 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 470 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 471 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 472 } 473 474 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 475 476 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 477 deqSelValidVec(1) := subDeqSelValidVec.get(0) 478 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 479 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 480 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 481 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 482 483 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 484 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 485 selOH := deqOH 486 } 487 } 488 else { 489 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 490 enq = VecInit(s0_doEnqSelValidVec), 491 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 492 ) 493 494 if (params.isAllComp || params.isAllSimp) { 495 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 496 enq = othersEntryEnqSelVec.get, 497 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 498 ) 499 500 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 501 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 502 selValid := false.B 503 selOH := 0.U.asTypeOf(selOH) 504 } else { 505 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 506 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 507 } 508 } 509 } 510 else { 511 othersEntryOldestSel := DontCare 512 513 deqCanIssue.zipWithIndex.foreach { case (req, i) => 514 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 515 } 516 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 517 if (params.numEnq == 2) { 518 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 519 } 520 521 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 522 enq = simpEntryEnqSelVec.get, 523 canIssue = simpAgeDetectRequest.get 524 ) 525 526 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 527 enq = compEntryEnqSelVec.get, 528 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 529 ) 530 531 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 532 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 533 selValid := false.B 534 selOH := 0.U.asTypeOf(selOH) 535 } else { 536 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 537 selOH := Cat( 538 compEntryOldestSel.get(i).bits, 539 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 540 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 541 ) 542 } 543 } 544 } 545 546 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 547 selValid := deqValid && deqBeforeDly(i).ready 548 selOH := deqOH 549 } 550 } 551 552 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 553 554 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 555 deqResp.valid := finalDeqSelValidVec(i) 556 deqResp.bits.resp := RespType.success 557 deqResp.bits.robIdx := DontCare 558 deqResp.bits.sqIdx.foreach(_ := DontCare) 559 deqResp.bits.lqIdx.foreach(_ := DontCare) 560 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 561 deqResp.bits.uopIdx.foreach(_ := DontCare) 562 } 563 564 //fuBusyTable 565 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 566 if(busyTableWrite.nonEmpty) { 567 val btwr = busyTableWrite.get 568 val btrd = busyTableRead.get 569 btwr.io.in.deqResp := toBusyTableDeqResp(i) 570 btwr.io.in.og0Resp := io.og0Resp(i) 571 btwr.io.in.og1Resp := io.og1Resp(i) 572 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 573 btrd.io.in.fuTypeRegVec := fuTypeVec 574 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 575 } 576 else { 577 fuBusyTableMask(i) := 0.U(params.numEntries.W) 578 } 579 } 580 581 //wbfuBusyTable write 582 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 583 if(busyTableWrite.nonEmpty) { 584 val btwr = busyTableWrite.get 585 val bt = busyTable.get 586 val dq = deqResp.get 587 btwr.io.in.deqResp := toBusyTableDeqResp(i) 588 btwr.io.in.og0Resp := io.og0Resp(i) 589 btwr.io.in.og1Resp := io.og1Resp(i) 590 bt := btwr.io.out.fuBusyTable 591 dq := btwr.io.out.deqRespSet 592 } 593 } 594 595 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 596 if (busyTableWrite.nonEmpty) { 597 val btwr = busyTableWrite.get 598 val bt = busyTable.get 599 val dq = deqResp.get 600 btwr.io.in.deqResp := toBusyTableDeqResp(i) 601 btwr.io.in.og0Resp := io.og0Resp(i) 602 btwr.io.in.og1Resp := io.og1Resp(i) 603 bt := btwr.io.out.fuBusyTable 604 dq := btwr.io.out.deqRespSet 605 } 606 } 607 608 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 609 if (busyTableWrite.nonEmpty) { 610 val btwr = busyTableWrite.get 611 val bt = busyTable.get 612 val dq = deqResp.get 613 btwr.io.in.deqResp := toBusyTableDeqResp(i) 614 btwr.io.in.og0Resp := io.og0Resp(i) 615 btwr.io.in.og1Resp := io.og1Resp(i) 616 bt := btwr.io.out.fuBusyTable 617 dq := btwr.io.out.deqRespSet 618 } 619 } 620 621 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 622 if (busyTableWrite.nonEmpty) { 623 val btwr = busyTableWrite.get 624 val bt = busyTable.get 625 val dq = deqResp.get 626 btwr.io.in.deqResp := toBusyTableDeqResp(i) 627 btwr.io.in.og0Resp := io.og0Resp(i) 628 btwr.io.in.og1Resp := io.og1Resp(i) 629 bt := btwr.io.out.fuBusyTable 630 dq := btwr.io.out.deqRespSet 631 } 632 } 633 634 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 635 if (busyTableWrite.nonEmpty) { 636 val btwr = busyTableWrite.get 637 val bt = busyTable.get 638 val dq = deqResp.get 639 btwr.io.in.deqResp := toBusyTableDeqResp(i) 640 btwr.io.in.og0Resp := io.og0Resp(i) 641 btwr.io.in.og1Resp := io.og1Resp(i) 642 bt := btwr.io.out.fuBusyTable 643 dq := btwr.io.out.deqRespSet 644 } 645 } 646 647 //wbfuBusyTable read 648 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 649 if(busyTableRead.nonEmpty) { 650 val btrd = busyTableRead.get 651 val bt = busyTable.get 652 btrd.io.in.fuBusyTable := bt 653 btrd.io.in.fuTypeRegVec := fuTypeVec 654 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 655 } 656 else { 657 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 658 } 659 } 660 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 661 if (busyTableRead.nonEmpty) { 662 val btrd = busyTableRead.get 663 val bt = busyTable.get 664 btrd.io.in.fuBusyTable := bt 665 btrd.io.in.fuTypeRegVec := fuTypeVec 666 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 667 } 668 else { 669 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 670 } 671 } 672 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 673 if (busyTableRead.nonEmpty) { 674 val btrd = busyTableRead.get 675 val bt = busyTable.get 676 btrd.io.in.fuBusyTable := bt 677 btrd.io.in.fuTypeRegVec := fuTypeVec 678 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 679 } 680 else { 681 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 682 } 683 } 684 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 685 if (busyTableRead.nonEmpty) { 686 val btrd = busyTableRead.get 687 val bt = busyTable.get 688 btrd.io.in.fuBusyTable := bt 689 btrd.io.in.fuTypeRegVec := fuTypeVec 690 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 691 } 692 else { 693 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 694 } 695 } 696 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 697 if (busyTableRead.nonEmpty) { 698 val btrd = busyTableRead.get 699 val bt = busyTable.get 700 btrd.io.in.fuBusyTable := bt 701 btrd.io.in.fuTypeRegVec := fuTypeVec 702 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 703 } 704 else { 705 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 706 } 707 } 708 709 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 710 wakeUpQueueOption.foreach { 711 wakeUpQueue => 712 val flush = Wire(new WakeupQueueFlush) 713 flush.redirect := io.flush 714 flush.ldCancel := io.ldCancel 715 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 716 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 717 wakeUpQueue.io.flush := flush 718 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 719 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 720 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 721 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 722 } 723 } 724 725 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 726 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 727 deq.bits.addrOH := finalDeqSelOHVec(i) 728 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 729 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 730 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 731 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 732 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 733 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 734 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 735 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 736 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 737 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 738 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 739 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 740 741 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 742 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 743 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 744 deq.bits.common.srcTimer.foreach(_ := DontCare) 745 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 746 deq.bits.common.src := DontCare 747 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 748 749 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 750 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 751 rf.foreach(_.addr := psrc) 752 rf.foreach(_.srcType := srcType) 753 } 754 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 755 sink := source 756 } 757 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 758 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 759 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 760 761 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 762 deq.bits.common.perfDebugInfo.selectTime := GTimer() 763 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 764 } 765 766 io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 767 NewPipelineConnect( 768 deq, deqDly, true.B, 769 false.B, 770 Option("Scheduler2DataPathPipe") 771 ) 772 } 773 if(backendParams.debugEn) { 774 dontTouch(io.deqDelay) 775 } 776 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 777 if (wakeUpQueues(i).nonEmpty) { 778 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 779 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 780 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 781 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 782 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 783 } else { 784 wakeup.valid := false.B 785 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 786 } 787 if (wakeUpQueues(i).nonEmpty) { 788 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 789 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 790 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 791 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 792 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 793 } 794 795 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 796 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 797 } 798 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 799 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 800 } 801 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 802 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 803 } 804 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 805 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 806 } 807 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 808 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 809 } 810 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 811 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 812 } 813 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 814 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 815 } 816 } 817 818 // Todo: better counter implementation 819 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 820 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 821 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 822 private val enqEntryValidCntDeq0 = PopCount( 823 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 824 ) 825 private val othersValidCntDeq0 = PopCount( 826 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 827 ) 828 private val enqEntryValidCntDeq1 = PopCount( 829 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 830 ) 831 private val othersValidCntDeq1 = PopCount( 832 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 833 ) 834 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 835 io.enq.map(_.bits.fuType).map(fuType => 836 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 837 } 838 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 839 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 840 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 841 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 842 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 843 for (i <- 0 until params.numEnq) { 844 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 845 } 846 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 847 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 848 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 849 } 850 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 851 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 852 853 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 854 io.status.empty := !Cat(validVec).orR 855 io.status.full := othersCanotIn 856 io.status.validCnt := PopCount(validVec) 857 858 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 859 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 860 } 861 862 // issue perf counter 863 // enq count 864 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 865 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 866 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 867 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 868 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 869 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 870 // valid count 871 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 872 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 873 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 874 // only split when more than 1 func type 875 if (params.getFuCfgs.size > 0) { 876 for (t <- FuType.functionNameMap.keys) { 877 val fuName = FuType.functionNameMap(t) 878 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 879 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 880 } 881 } 882 } 883 // ready instr count 884 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 885 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 886 // only split when more than 1 func type 887 if (params.getFuCfgs.size > 0) { 888 for (t <- FuType.functionNameMap.keys) { 889 val fuName = FuType.functionNameMap(t) 890 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 891 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 892 } 893 } 894 } 895 896 // deq instr count 897 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 898 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 899 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 900 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 901 902 // deq instr data source count 903 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 904 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 905 }.reduce(_ +& _)) 906 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 907 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 908 }.reduce(_ +& _)) 909 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 910 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 911 }.reduce(_ +& _)) 912 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 913 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 914 }.reduce(_ +& _)) 915 916 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 917 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 918 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 919 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 920 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 921 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 922 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 923 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 924 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 925 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 926 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 927 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 928 929 // deq instr data source count for each futype 930 for (t <- FuType.functionNameMap.keys) { 931 val fuName = FuType.functionNameMap(t) 932 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 933 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 934 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 935 }.reduce(_ +& _)) 936 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 937 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 938 }.reduce(_ +& _)) 939 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 940 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 941 }.reduce(_ +& _)) 942 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 943 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 944 }.reduce(_ +& _)) 945 946 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 947 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 948 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 949 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 950 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 951 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 952 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 953 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 954 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 955 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 956 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 957 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 958 } 959 } 960} 961 962class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 963 val fastMatch = UInt(backendParams.LduCnt.W) 964 val fastImm = UInt(12.W) 965} 966 967class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 968 969class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 970 extends IssueQueueImp(wrapper) 971{ 972 io.suggestName("none") 973 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 974 975 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 976 deq.bits.common.pc.foreach(_ := DontCare) 977 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 978 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 979 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 980 deq.bits.common.predictInfo.foreach(x => { 981 x.target := DontCare 982 x.taken := deqEntryVec(i).bits.payload.pred_taken 983 }) 984 // for std 985 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 986 // for i2f 987 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 988 }} 989} 990 991class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 992 extends IssueQueueImp(wrapper) 993{ 994 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 995 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 996 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 997 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 998 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 999 }} 1000} 1001 1002class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1003 extends IssueQueueImp(wrapper) 1004{ 1005 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1006 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1007 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1008 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1009 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1010 }} 1011} 1012 1013class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1014 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1015 1016 // TODO: is still needed? 1017 val checkWait = new Bundle { 1018 val stIssuePtr = Input(new SqPtr) 1019 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1020 } 1021 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1022 1023 // load wakeup 1024 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1025 1026 // vector 1027 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1028 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1029} 1030 1031class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1032 val memIO = Some(new IssueQueueMemBundle) 1033} 1034 1035class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1036 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1037 1038 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1039 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1040 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1041 1042 io.suggestName("none") 1043 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1044 private val memIO = io.memIO.get 1045 1046 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1047 1048 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1049 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1050 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1051 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1052 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1053 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1054 slowResp.bits.fuType := DontCare 1055 } 1056 1057 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1058 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1059 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1060 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1061 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1062 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1063 fastResp.bits.fuType := DontCare 1064 } 1065 1066 // load wakeup 1067 val loadWakeUpIter = memIO.loadWakeUp.iterator 1068 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1069 if (param.hasLoadExu) { 1070 require(wakeUpQueues(i).isEmpty) 1071 val uop = loadWakeUpIter.next() 1072 1073 wakeup.valid := GatedValidRegNext(uop.fire) 1074 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1075 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1076 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1077 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1078 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1079 wakeup.bits.pdest := RegNext(uop.bits.pdest) 1080 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1081 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1082 1083 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1084 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1085 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1086 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1087 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1088 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest))) 1089 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1090 1091 wakeup.bits.is0Lat := 0.U 1092 } 1093 } 1094 require(!loadWakeUpIter.hasNext) 1095 1096 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1097 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1098 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1099 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1100 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1101 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1102 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1103 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1104 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1105 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1106 } 1107} 1108 1109class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1110 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1111 1112 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1113 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1114 1115 io.suggestName("none") 1116 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1117 private val memIO = io.memIO.get 1118 1119 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1120 1121 for (i <- entries.io.enq.indices) { 1122 entries.io.enq(i).bits.status match { case enqData => 1123 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1124 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1125 // MemAddrIQ also handle vector insts 1126 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1127 enqData.blocked := false.B 1128 } 1129 } 1130 1131 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1132 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1133 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1134 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1135 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1136 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1137 slowResp.bits.fuType := DontCare 1138 slowResp.bits.uopIdx.get := DontCare 1139 } 1140 1141 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1142 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1143 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1144 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1145 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1146 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1147 fastResp.bits.fuType := DontCare 1148 fastResp.bits.uopIdx.get := DontCare 1149 } 1150 1151 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1152 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1153 1154 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1155 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1156 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1157 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1158 if (params.isVecLduIQ) { 1159 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1160 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1161 } 1162 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1163 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1164 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1165 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1166 } 1167 1168 io.vecLoadIssueResp.foreach(dontTouch(_)) 1169} 1170