feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

area(backend): only use startAddr in pcMem

area(backend): only pipe wakeupFromIQ and wakeupFromWB once

area(Backend): merge pcMem and pcTargetMem

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

fix(Backend): add vecLoadFinalIssueResp

feat(rv64v): support first only fault instruction

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

power(backend): add clock gate for Rob and IssueQueue (#3602)

power(IssueQueue): add clock gate for deqDelay reg (#3583)

perf(IssueQueue): add 'wen' to the valid condition of each wbBusyTableWrite (#3566)

fix(IssueQueue): fix bug of iq's enq ready when simpEntry is small (#3507)

timing(Backend): add OG2 stage for vector mem (#3482)

fix(IssueQueue): width of validCnt

IssueQueue: only trans valid but not issued entry for fix ldCancel timing

IssueQueue: fix toBusyTableDeqResp's valid for better performance

IssueQueue: remove deqDelay clock gate for fix timing

IssueQueue, RegCache: fix conflict after rebase

Scheduler, RegCache: add RegCacheTagTable to read reg cache state before entering issue queue

IssueQueue: receive rcIdx from wakeup, add new data source type regcache

Backend: add reg cache data writing back path

DataPath: add RegCache