1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19import xiangshan.backend.fu.vector.Bundles.VSew 20 21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 override def shouldBeInlined: Boolean = false 23 24 implicit val iqParams: IssueBlockParams = params 25 lazy val module: IssueQueueImp = iqParams.schdType match { 26 case IntScheduler() => new IssueQueueIntImp(this) 27 case FpScheduler() => new IssueQueueFpImp(this) 28 case VfScheduler() => new IssueQueueVfImp(this) 29 case MemScheduler() => 30 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 31 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 32 else new IssueQueueIntImp(this) 33 case _ => null 34 } 35} 36 37class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 38 val empty = Output(Bool()) 39 val full = Output(Bool()) 40 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 41 val leftVec = Output(Vec(numEnq + 1, Bool())) 42} 43 44class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 45 46class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 47 // Inputs 48 val flush = Flipped(ValidIO(new Redirect)) 49 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 50 51 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 53 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 57 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 58 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 59 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 60 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 61 val vlIsZero = Input(Bool()) 62 val vlIsVlmax = Input(Bool()) 63 val og0Cancel = Input(ExuOH(backendParams.numExu)) 64 val og1Cancel = Input(ExuOH(backendParams.numExu)) 65 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 66 67 // Outputs 68 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 69 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 70 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 71 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 72 73 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 74 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 75} 76 77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 78 extends LazyModuleImp(wrapper) 79 with HasXSParameter { 80 81 override def desiredName: String = s"${params.getIQName}" 82 83 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 84 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 85 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 86 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 87 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 88 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 89 90 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 91 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 92 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 93 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 94 95 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 96 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 97 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 98 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 99 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 100 101 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 102 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 103 lazy val io = IO(new IssueQueueIO()) 104 105 // Modules 106 val entries = Module(new Entries) 107 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 108 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 109 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 110 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 111 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 112 val fpWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 113 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 114 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 115 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 116 val v0WbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 117 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 118 val vlWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 119 120 class WakeupQueueFlush extends Bundle { 121 val redirect = ValidIO(new Redirect) 122 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 123 val og0Fail = Output(Bool()) 124 val og1Fail = Output(Bool()) 125 } 126 127 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 128 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 129 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 130 val ogFailFlush = stage match { 131 case 1 => flush.og0Fail 132 case 2 => flush.og1Fail 133 case _ => false.B 134 } 135 redirectFlush || loadDependencyFlush || ogFailFlush 136 } 137 138 private def modificationFunc(exuInput: ExuInput): ExuInput = { 139 val newExuInput = WireDefault(exuInput) 140 newExuInput.loadDependency match { 141 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 142 case None => 143 } 144 newExuInput 145 } 146 147 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 148 val lastExuInput = WireDefault(exuInput) 149 val newExuInput = WireDefault(newInput) 150 newExuInput.elements.foreach { case (name, data) => 151 if (lastExuInput.elements.contains(name)) { 152 data := lastExuInput.elements(name) 153 } 154 } 155 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 156 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 157 } 158 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 159 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 160 } 161 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 162 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 163 } 164 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 165 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 166 } 167 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 168 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 169 } 170 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 171 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 172 } 173 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 174 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 175 } 176 newExuInput 177 } 178 179 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 180 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 181 ))} 182 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 183 184 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 185 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 186 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 187 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 188 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 189 190 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 191 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 192 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 193 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 194 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 195 196 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 197 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 198 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 199 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 200 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 201 202 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 209 val s0_enqValidVec = io.enq.map(_.valid) 210 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 211 val s0_enqNotFlush = !io.flush.valid 212 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 213 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 214 215 216 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 217 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 218 219 val validVec = VecInit(entries.io.valid.asBools) 220 val canIssueVec = VecInit(entries.io.canIssue.asBools) 221 dontTouch(canIssueVec) 222 val deqFirstIssueVec = entries.io.isFirstIssue 223 224 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 225 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 226 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 227 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 228 // (entryIdx)(srcIdx)(exuIdx) 229 val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH 230 // (deqIdx)(srcIdx)(exuIdx) 231 val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 232 233 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 234 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 235 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 236 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 237 238 //deq 239 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 240 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 241 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 242 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 243 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 244 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 245 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 246 247 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 248 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 249 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 250 251 //trans 252 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 253 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 254 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 255 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 256 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 257 258 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 259 // as vf exu's min latency is 1, we do not need consider og0cancel 260 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 261 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 262 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 263 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 264 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 265 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 266 } else { 267 w := w_src 268 } 269 } 270 271 /** 272 * Connection of [[entries]] 273 */ 274 entries.io match { case entriesIO: EntriesIO => 275 entriesIO.flush := io.flush 276 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 277 enq.valid := s0_doEnqSelValidVec(enqIdx) 278 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 279 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 280 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 281 for(j <- 0 until numLsrc) { 282 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 283 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 284 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 285 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 286 SrcState.rdy, 287 s0_enqBits(enqIdx).srcState(j)) 288 } else { 289 s0_enqBits(enqIdx).srcState(j) 290 }) 291 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 292 MuxCase(DataSource.reg, Seq( 293 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 294 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 295 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 296 )) 297 } else { 298 MuxCase(DataSource.reg, Seq( 299 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 300 )) 301 }) 302 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 303 if(params.hasIQWakeUp) { 304 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 305 } 306 } 307 enq.bits.status.blocked := false.B 308 enq.bits.status.issued := false.B 309 enq.bits.status.firstIssue := false.B 310 enq.bits.status.issueTimer := "b11".U 311 enq.bits.status.deqPortIdx := 0.U 312 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 313 enq.bits.payload := s0_enqBits(enqIdx) 314 } 315 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 316 og0Resp := io.og0Resp(i) 317 } 318 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 319 og1Resp := io.og1Resp(i) 320 } 321 if (params.inVfSchd) { 322 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 323 og2Resp := io.og2Resp.get(i) 324 } 325 } 326 if (params.isLdAddrIQ || params.isHyAddrIQ) { 327 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 328 finalIssueResp := io.finalIssueResp.get(i) 329 } 330 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 331 memAddrIssueResp := io.memAddrIssueResp.get(i) 332 } 333 } 334 if (params.isVecLduIQ) { 335 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 336 resp := io.vecLoadIssueResp.get(i) 337 } 338 } 339 for(deqIdx <- 0 until params.numDeq) { 340 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 341 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 342 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 343 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 344 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 345 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 346 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 347 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 348 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 349 } 350 entriesIO.wakeUpFromWB := io.wakeupFromWB 351 entriesIO.wakeUpFromIQ := wakeupFromIQ 352 entriesIO.vlIsZero := io.vlIsZero 353 entriesIO.vlIsVlmax := io.vlIsVlmax 354 entriesIO.og0Cancel := io.og0Cancel 355 entriesIO.og1Cancel := io.og1Cancel 356 entriesIO.ldCancel := io.ldCancel 357 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 358 //output 359 fuTypeVec := entriesIO.fuType 360 deqEntryVec := entriesIO.deqEntry 361 cancelDeqVec := entriesIO.cancelDeqVec 362 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 363 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 364 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 365 } 366 367 368 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 369 370 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 371 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 372 ).reverse) 373 374 // if deq port can accept the uop 375 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 376 Cat(fuTypeVec.map(fuType => 377 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 378 ).reverse) 379 } 380 381 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 382 fuTypeVec.map(fuType => 383 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 384 } 385 386 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 387 val mergeFuBusy = { 388 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 389 else canIssueVec.asUInt 390 } 391 val mergeIntWbBusy = { 392 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 393 else mergeFuBusy 394 } 395 val mergefpWbBusy = { 396 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 397 else mergeIntWbBusy 398 } 399 val mergeVfWbBusy = { 400 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 401 else mergefpWbBusy 402 } 403 val mergeV0WbBusy = { 404 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 405 else mergeVfWbBusy 406 } 407 val mergeVlWbBusy = { 408 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 409 else mergeV0WbBusy 410 } 411 merge := mergeVlWbBusy 412 } 413 414 deqCanIssue.zipWithIndex.foreach { case (req, i) => 415 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 416 } 417 dontTouch(fuTypeVec) 418 dontTouch(canIssueMergeAllBusy) 419 dontTouch(deqCanIssue) 420 421 if (params.numDeq == 2) { 422 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 423 } 424 425 if (params.numDeq == 2 && params.deqFuSame) { 426 val subDeqPolicy = Module(new DeqPolicy()) 427 428 enqEntryOldestSel := DontCare 429 430 if (params.isAllComp || params.isAllSimp) { 431 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 432 enq = othersEntryEnqSelVec.get, 433 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 434 ) 435 othersEntryOldestSel(1) := DontCare 436 437 subDeqPolicy.io.request := subDeqRequest.get 438 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 439 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 440 } 441 else { 442 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 443 simpAgeDetectRequest.get(1) := DontCare 444 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 445 if (params.numEnq == 2) { 446 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 447 } 448 449 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 450 enq = simpEntryEnqSelVec.get, 451 canIssue = simpAgeDetectRequest.get 452 ) 453 454 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 455 enq = compEntryEnqSelVec.get, 456 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 457 ) 458 compEntryOldestSel.get(1) := DontCare 459 460 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 461 othersEntryOldestSel(0).bits := Cat( 462 compEntryOldestSel.get(0).bits, 463 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 464 ) 465 othersEntryOldestSel(1) := DontCare 466 467 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 468 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 469 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 470 } 471 472 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 473 474 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 475 deqSelValidVec(1) := subDeqSelValidVec.get(0) 476 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 477 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 478 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 479 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 480 481 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 482 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 483 selOH := deqOH 484 } 485 } 486 else { 487 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 488 enq = VecInit(s0_doEnqSelValidVec), 489 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 490 ) 491 492 if (params.isAllComp || params.isAllSimp) { 493 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 494 enq = othersEntryEnqSelVec.get, 495 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 496 ) 497 498 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 499 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 500 selValid := false.B 501 selOH := 0.U.asTypeOf(selOH) 502 } else { 503 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 504 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 505 } 506 } 507 } 508 else { 509 othersEntryOldestSel := DontCare 510 511 deqCanIssue.zipWithIndex.foreach { case (req, i) => 512 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 513 } 514 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 515 if (params.numEnq == 2) { 516 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 517 } 518 519 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 520 enq = simpEntryEnqSelVec.get, 521 canIssue = simpAgeDetectRequest.get 522 ) 523 524 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 525 enq = compEntryEnqSelVec.get, 526 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 527 ) 528 529 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 530 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 531 selValid := false.B 532 selOH := 0.U.asTypeOf(selOH) 533 } else { 534 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 535 selOH := Cat( 536 compEntryOldestSel.get(i).bits, 537 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 538 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 539 ) 540 } 541 } 542 } 543 544 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 545 selValid := deqValid && deqBeforeDly(i).ready 546 selOH := deqOH 547 } 548 } 549 550 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 551 552 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 553 deqResp.valid := finalDeqSelValidVec(i) 554 deqResp.bits.resp := RespType.success 555 deqResp.bits.robIdx := DontCare 556 deqResp.bits.sqIdx.foreach(_ := DontCare) 557 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 558 deqResp.bits.uopIdx.foreach(_ := DontCare) 559 } 560 561 //fuBusyTable 562 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 563 if(busyTableWrite.nonEmpty) { 564 val btwr = busyTableWrite.get 565 val btrd = busyTableRead.get 566 btwr.io.in.deqResp := toBusyTableDeqResp(i) 567 btwr.io.in.og0Resp := io.og0Resp(i) 568 btwr.io.in.og1Resp := io.og1Resp(i) 569 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 570 btrd.io.in.fuTypeRegVec := fuTypeVec 571 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 572 } 573 else { 574 fuBusyTableMask(i) := 0.U(params.numEntries.W) 575 } 576 } 577 578 //wbfuBusyTable write 579 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 580 if(busyTableWrite.nonEmpty) { 581 val btwr = busyTableWrite.get 582 val bt = busyTable.get 583 val dq = deqResp.get 584 btwr.io.in.deqResp := toBusyTableDeqResp(i) 585 btwr.io.in.og0Resp := io.og0Resp(i) 586 btwr.io.in.og1Resp := io.og1Resp(i) 587 bt := btwr.io.out.fuBusyTable 588 dq := btwr.io.out.deqRespSet 589 } 590 } 591 592 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 593 if (busyTableWrite.nonEmpty) { 594 val btwr = busyTableWrite.get 595 val bt = busyTable.get 596 val dq = deqResp.get 597 btwr.io.in.deqResp := toBusyTableDeqResp(i) 598 btwr.io.in.og0Resp := io.og0Resp(i) 599 btwr.io.in.og1Resp := io.og1Resp(i) 600 bt := btwr.io.out.fuBusyTable 601 dq := btwr.io.out.deqRespSet 602 } 603 } 604 605 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 606 if (busyTableWrite.nonEmpty) { 607 val btwr = busyTableWrite.get 608 val bt = busyTable.get 609 val dq = deqResp.get 610 btwr.io.in.deqResp := toBusyTableDeqResp(i) 611 btwr.io.in.og0Resp := io.og0Resp(i) 612 btwr.io.in.og1Resp := io.og1Resp(i) 613 bt := btwr.io.out.fuBusyTable 614 dq := btwr.io.out.deqRespSet 615 } 616 } 617 618 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 619 if (busyTableWrite.nonEmpty) { 620 val btwr = busyTableWrite.get 621 val bt = busyTable.get 622 val dq = deqResp.get 623 btwr.io.in.deqResp := toBusyTableDeqResp(i) 624 btwr.io.in.og0Resp := io.og0Resp(i) 625 btwr.io.in.og1Resp := io.og1Resp(i) 626 bt := btwr.io.out.fuBusyTable 627 dq := btwr.io.out.deqRespSet 628 } 629 } 630 631 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 632 if (busyTableWrite.nonEmpty) { 633 val btwr = busyTableWrite.get 634 val bt = busyTable.get 635 val dq = deqResp.get 636 btwr.io.in.deqResp := toBusyTableDeqResp(i) 637 btwr.io.in.og0Resp := io.og0Resp(i) 638 btwr.io.in.og1Resp := io.og1Resp(i) 639 bt := btwr.io.out.fuBusyTable 640 dq := btwr.io.out.deqRespSet 641 } 642 } 643 644 //wbfuBusyTable read 645 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 646 if(busyTableRead.nonEmpty) { 647 val btrd = busyTableRead.get 648 val bt = busyTable.get 649 btrd.io.in.fuBusyTable := bt 650 btrd.io.in.fuTypeRegVec := fuTypeVec 651 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 652 } 653 else { 654 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 655 } 656 } 657 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 658 if (busyTableRead.nonEmpty) { 659 val btrd = busyTableRead.get 660 val bt = busyTable.get 661 btrd.io.in.fuBusyTable := bt 662 btrd.io.in.fuTypeRegVec := fuTypeVec 663 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 664 } 665 else { 666 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 667 } 668 } 669 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 670 if (busyTableRead.nonEmpty) { 671 val btrd = busyTableRead.get 672 val bt = busyTable.get 673 btrd.io.in.fuBusyTable := bt 674 btrd.io.in.fuTypeRegVec := fuTypeVec 675 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 676 } 677 else { 678 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 679 } 680 } 681 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 682 if (busyTableRead.nonEmpty) { 683 val btrd = busyTableRead.get 684 val bt = busyTable.get 685 btrd.io.in.fuBusyTable := bt 686 btrd.io.in.fuTypeRegVec := fuTypeVec 687 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 688 } 689 else { 690 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 691 } 692 } 693 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 694 if (busyTableRead.nonEmpty) { 695 val btrd = busyTableRead.get 696 val bt = busyTable.get 697 btrd.io.in.fuBusyTable := bt 698 btrd.io.in.fuTypeRegVec := fuTypeVec 699 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 700 } 701 else { 702 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 703 } 704 } 705 706 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 707 wakeUpQueueOption.foreach { 708 wakeUpQueue => 709 val flush = Wire(new WakeupQueueFlush) 710 flush.redirect := io.flush 711 flush.ldCancel := io.ldCancel 712 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 713 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 714 wakeUpQueue.io.flush := flush 715 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 716 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 717 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 718 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 719 } 720 } 721 722 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 723 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 724 deq.bits.addrOH := finalDeqSelOHVec(i) 725 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 726 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 727 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 728 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 729 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 730 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 731 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 732 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 733 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 734 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 735 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 736 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 737 738 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 739 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 740 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 741 deq.bits.common.srcTimer.foreach(_ := DontCare) 742 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 743 deq.bits.common.src := DontCare 744 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 745 746 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 747 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 748 rf.foreach(_.addr := psrc) 749 rf.foreach(_.srcType := srcType) 750 } 751 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 752 sink := source 753 } 754 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 755 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 756 757 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 758 deq.bits.common.perfDebugInfo.selectTime := GTimer() 759 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 760 } 761 762 io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 763 NewPipelineConnect( 764 deq, deqDly, deqDly.valid, 765 false.B, 766 Option("Scheduler2DataPathPipe") 767 ) 768 } 769 if(backendParams.debugEn) { 770 dontTouch(io.deqDelay) 771 } 772 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 773 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 774 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 775 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 776 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 777 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 778 } else if (wakeUpQueues(i).nonEmpty) { 779 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 780 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 781 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 782 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 783 } else { 784 wakeup.valid := false.B 785 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 786 wakeup.bits.is0Lat := 0.U 787 } 788 if (wakeUpQueues(i).nonEmpty) { 789 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 790 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 791 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 792 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 793 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 794 } 795 796 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 797 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 798 } 799 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 800 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 801 } 802 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 803 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 804 } 805 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 806 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 807 } 808 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 809 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 810 } 811 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 812 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 813 } 814 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 815 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 816 } 817 } 818 819 // Todo: better counter implementation 820 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 821 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 822 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 823 private val enqEntryValidCntDeq0 = PopCount( 824 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 825 ) 826 private val othersValidCntDeq0 = PopCount( 827 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 828 ) 829 private val enqEntryValidCntDeq1 = PopCount( 830 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 831 ) 832 private val othersValidCntDeq1 = PopCount( 833 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 834 ) 835 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 836 io.enq.map(_.bits.fuType).map(fuType => 837 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 838 } 839 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 840 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 841 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 842 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 843 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 844 for (i <- 0 until params.numEnq) { 845 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 846 } 847 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 848 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 849 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 850 } 851 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 852 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 853 854 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 855 io.status.empty := !Cat(validVec).orR 856 io.status.full := othersCanotIn 857 io.status.validCnt := PopCount(validVec) 858 859 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 860 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 861 } 862 863 // issue perf counter 864 // enq count 865 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 866 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 867 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 868 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 869 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 870 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 871 // valid count 872 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 873 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 874 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 875 // only split when more than 1 func type 876 if (params.getFuCfgs.size > 0) { 877 for (t <- FuType.functionNameMap.keys) { 878 val fuName = FuType.functionNameMap(t) 879 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 880 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 881 } 882 } 883 } 884 // ready instr count 885 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 886 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 887 // only split when more than 1 func type 888 if (params.getFuCfgs.size > 0) { 889 for (t <- FuType.functionNameMap.keys) { 890 val fuName = FuType.functionNameMap(t) 891 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 892 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 893 } 894 } 895 } 896 897 // deq instr count 898 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 899 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 900 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 901 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 902 903 // deq instr data source count 904 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 905 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 906 }.reduce(_ +& _)) 907 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 908 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 909 }.reduce(_ +& _)) 910 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 911 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 912 }.reduce(_ +& _)) 913 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 914 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 915 }.reduce(_ +& _)) 916 917 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 918 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 919 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 920 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 921 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 922 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 923 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 924 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 925 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 926 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 927 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 928 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 929 930 // deq instr data source count for each futype 931 for (t <- FuType.functionNameMap.keys) { 932 val fuName = FuType.functionNameMap(t) 933 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 934 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 935 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 936 }.reduce(_ +& _)) 937 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 938 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 939 }.reduce(_ +& _)) 940 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 941 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 942 }.reduce(_ +& _)) 943 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 944 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 945 }.reduce(_ +& _)) 946 947 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 948 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 949 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 950 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 951 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 952 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 953 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 954 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 955 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 956 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 957 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 958 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 959 } 960 } 961} 962 963class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 964 val fastMatch = UInt(backendParams.LduCnt.W) 965 val fastImm = UInt(12.W) 966} 967 968class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 969 970class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 971 extends IssueQueueImp(wrapper) 972{ 973 io.suggestName("none") 974 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 975 976 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 977 deq.bits.common.pc.foreach(_ := DontCare) 978 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 979 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 980 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 981 deq.bits.common.predictInfo.foreach(x => { 982 x.target := DontCare 983 x.taken := deqEntryVec(i).bits.payload.pred_taken 984 }) 985 // for std 986 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 987 // for i2f 988 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 989 }} 990} 991 992class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 993 extends IssueQueueImp(wrapper) 994{ 995 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 996 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 997 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 998 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 999 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1000 }} 1001} 1002 1003class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1004 extends IssueQueueImp(wrapper) 1005{ 1006 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1007 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1008 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1009 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1010 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1011 }} 1012} 1013 1014class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1015 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1016 1017 // TODO: is still needed? 1018 val checkWait = new Bundle { 1019 val stIssuePtr = Input(new SqPtr) 1020 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1021 } 1022 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1023 1024 // load wakeup 1025 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1026 1027 // vector 1028 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 1029 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 1030} 1031 1032class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1033 val memIO = Some(new IssueQueueMemBundle) 1034} 1035 1036class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1037 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1038 1039 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1040 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1041 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1042 1043 io.suggestName("none") 1044 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1045 private val memIO = io.memIO.get 1046 1047 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1048 1049 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1050 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1051 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1052 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1053 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1054 slowResp.bits.fuType := DontCare 1055 } 1056 1057 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1058 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1059 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1060 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1061 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1062 fastResp.bits.fuType := DontCare 1063 } 1064 1065 // load wakeup 1066 val loadWakeUpIter = memIO.loadWakeUp.iterator 1067 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1068 if (param.hasLoadExu) { 1069 require(wakeUpQueues(i).isEmpty) 1070 val uop = loadWakeUpIter.next() 1071 1072 wakeup.valid := GatedValidRegNext(uop.fire) 1073 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1074 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1075 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1076 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1077 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1078 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1079 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1080 1081 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1082 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1083 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1084 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1085 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1086 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1087 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1088 1089 wakeup.bits.is0Lat := 0.U 1090 } 1091 } 1092 require(!loadWakeUpIter.hasNext) 1093 1094 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1095 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1096 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1097 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1098 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1099 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1100 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1101 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1102 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1103 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1104 } 1105} 1106 1107class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1108 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1109 1110 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1111 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1112 1113 io.suggestName("none") 1114 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1115 private val memIO = io.memIO.get 1116 1117 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1118 1119 for (i <- entries.io.enq.indices) { 1120 entries.io.enq(i).bits.status match { case enqData => 1121 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1122 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1123 // MemAddrIQ also handle vector insts 1124 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1125 enqData.blocked := false.B 1126 } 1127 } 1128 1129 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1130 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1131 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1132 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1133 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1134 slowResp.bits.fuType := DontCare 1135 slowResp.bits.uopIdx.get := DontCare 1136 } 1137 1138 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1139 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1140 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1141 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1142 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1143 fastResp.bits.fuType := DontCare 1144 fastResp.bits.uopIdx.get := DontCare 1145 } 1146 1147 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1148 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1149 1150 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1151 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1152 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1153 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1154 if (params.isVecLduIQ) { 1155 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1156 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1157 } 1158 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1159 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1160 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1161 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1162 } 1163 1164 io.vecLoadIssueResp.foreach(dontTouch(_)) 1165} 1166